MEDEA+ 2T101: sSOI for High-Performance ICs
Posted date : Jul 11, 2005

The objective is to provide an industrial source of large diameter strained SOI wafers within 3 years.

A “Phase 2” MEDEA+ project, 2T101, known as SILONIS is currently ramping up. The project, which is lead by Soitec, involves 15 partners, including suppliers and IC makers active in four different European countries.

The goal is to build “…a strained SOI technological platform gathering the main European actors in substrates, metrology and ICs in order to hasten the development of high mobility (strained) SOI wafers and to shorten their introduction in a IC fab environment. The substrate platform encompasses the processing compatibility of these new substrates with sub-65nm technology in the industrial environment of IC makers. High mobility “strained Si” and “SOI” are two breakthroughs that the consortium wish to combine in one single technology platform for high performance ICs.”

In addition to the material-related activities, the project will also encompass device development.
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