Substrate strategies for high-performance and low-power applications at 45 nm

Substrate strategies for high-performance and low-power applications at 45 nm

Two distinct technical strategies for advanced substrates will mark the 45nm node. One will be focused on high performance, the other driven by system-on-chip (SOC) applications, including low power, portable RF applications.

The high performance path will drive the most advanced substrates and material innovations. Engineered substrate solutions include ultra-thin (UT) SOI, mobility enhancing substrates like strained SOI (sSOI) in addition to local strain techniques, as well as improved thermal dissipation to reduce the impact of hot spot impact. While device architectures are likely to remain planar, FinFETs are on the horizon for the 32nm node for the most aggressive IC players. The relationship between engineered wafers and device architecture will grow even tighter. Partially depleted approaches will push the mobility enhancing substrates while others may switch to ultra-thin fully depleted SOI in order to improve electrostatic device characteristics. Each way presents its own set of technical advantages and challenges.

For those pursuing advanced RF SOCs, options include high impedance SOI substrates with a high resistivity handle wafer, while SOI with ultra thin buried oxide ( < 50nm ) will enable IC architectures where n and p regions are defined in the handle substrate for back bias generation through the buried oxide. Rather than focusing on attaining the highest performance, these SOI CMOS solutions will target the lowest power consumption and longest battery lifetime. Low standby and low operating power devices will be built by taking full advantage of dielectric isolation, while high resistivity substrates will substantially improve performance of passive components such as inductors that are placed directly on the silicon chip. •

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