Zero Capacitor Embedded Memory Technology Reverses SOI vs. Bulk Economics
Posted date : Jul 11, 2005

Z-RAM + SOI can save > 40%.

There is no doubt today that the industry, led by the microprocessor segment, is moving to take advantage of the lower power consumption and higher performance of SOI compared to bulk wafers.
SOI offers substantial technical advantages on speed, power and even the ability to integrate RF and is being chosen where these benefits justify the necessarily higher cost of SOI wafers.
A new embedded memory technology – developed by Innovative Silicon Inc – is overturning the conventional wisdom that SOI is a better, but more costly solution, and in future, chips fabricated on SOI could not only have these speed and power advantages, but should also be significantly lower cost.

Z-RAM memories harness SOI’s Floating Body effect, resulting in a true capacitor-less, single transistor DRAM (Zero capacitor DRAM) -capable of achieving five times the density of current embedded SRAM, yet requiring no new materials or extra mask steps.

As an example; if (as is common) memory occupies around 70% of chip die area using embedded SRAM, then by substituting Z-RAM which is five times as dense, die size can be reduced by around 56%. Since the higher wafer price adds typically less than 15% to the processed silicon cost of SOI, the net savings by using SOI (and Z-RAM) compared to bulk silicon should be over 40% – truly a reversal of the SOI vs. bulk economics. •

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