First ASIC design kit for 90nm SOI process
Posted date : Dec 7, 2005

Soisic solution enables any ASIC designer using industry-standard EDA tools to move transparently into SOI



Until now, any company doing SOI chips has been using their own internal tools and design flows: there was no standard SOI ASIC design kit available. This effectively shut out fabless companies and complicated things for those companies having wide product arrays.

Working with companies pioneering SOI-based chips, Soisic has developed extensive design expertise and intellectual property (IP). We are now able to make that IP available to any ASIC designer that wants to move into SOI. For a simple licensing fee, a design team can transparently integrate the SOI-specific design considerations into the design flow – without a special understanding of SOI (things like the history effect, for example) and the differences with bulk. No additional investment in time, training or libraries is needed.

The Soisic design kit includes three standard, footprint compatible cell libraries (600 cells), addressing the multi-threshold option (low-Vt, standard- Vt and high-Vt) offered in the SOI 90nm process. Each library is characterized at nominal 1V power- supply voltage; 0.8V characterization is available for static and dynamic low-power usage. The SOI 90-nm process uses partially-depleted transistors.

The design-kit includes a single-port SRAM compiler and a set of standard I/O. Dual-port SRAM, ROM and register file compilers are also available.

The robustness of the libraries has been proven in extensive commercial deployment. The complete design kit IP has been validated on a complex test chip featuring 2.6 million gates (see illustration), designed using a standard EDA flow and common commercial tools. The test chip proved silicon right at its first tapeout, and silicon measurements accurately correlated with simulation results.

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