More and More Strain
Posted date : Dec 7, 2005

Dr. Yoshimi reviews some recent approaches to strained SOI implementation

Implementing strain into the channel of MOSFETs has become mainstream technology for high-performance CMOS-FETs. Process induced uniaxial stress is being used today to boost carrier mobilities of sub-µm devices and thus improve IC performance.

Soitec’s Smart Cut™ technology has been demonstrated for the fabrication of 300-mm sSOI (strained-SOI), in which the Si lattice is uniformly stretched by 0.8%. By using sSOI, 45nm (gate-length) MOSFETs have been demonstrated, exhibiting higher performance than conventional SOI MOSFETs (A.Thean et al.(Freescale), VLSI Symp. 2005), thanks to a 60% enhancement in electron mobility.

Device engineers use various ways to implement local strain, by using stressors like embedded SiGe at the source and drain (T.Ghani et al. (Intel), IEDM 2003) or stress liner at the gate-sidewall (K. Goto et al. (Fujitsu), IEDM 2004).

At SSDM, held in September 2005, A.Wei et al. (AMD) reported on the result of simultaneously implementing the embedded-SiGe structure and the gate sidewall stress-liner. It was confirmed that the performance enhancement in SOI PMOS-FETs was “additive”.

The combination of HOT (hybrid-orientation technology) and stressors is another option to enhance device current drive. In HOT, one can utilize both the (100) and the (110) crystal orientations so as to individually maximize the mobility for NMOS and PMOS. Q.Ouyang et al. (IBM, VLSI Symp.2005), demonstrated that performance of HOT substrates can be enhanced more than in the case where only a (100) Si surface is used.

In the coming conferences, device engineers will be discussing what the best solution is for implementing strain among these options. Further scaling beyond the 65-nm technology node will impose limitations on process induced stressor techniques thus reducing its mobility enhancing efficiency. Soitec’s wafer strain will provide the needed strain for future technologies with the advantage of being device-geometry independent and additive to existing stressor techniques.

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