Overall the cost of an SOI chip is not higher than bulk and may even be lower, depending on the application.
Cost is an important factor when developing a chip and going to production. Users of bulk substrates may ask how they can manage the added cost of the SOI substrate if they were to switch their chip from bulk to SOI CMOS.
As SOI brings higher speed and/or enables a reduction in power consumption, one can argue that these advantages bring an added value and should allow for a higher sales price of the chip. But for some, that is not enough.
They argue that their applications are so low-cost and their markets so cost driven that their customers are not ready to pay a premium for SOI. However, if they were to look at the final cost of the chip or even the cost of the system in which the chip is going to be integrated rather than just the price of the SOI substrate and the cost of the process manufacturing, chances are they would have very different perspectives.
At the 90nm node, for a given speed (frequency), we have demonstrated that using SOI in the logic core with standard cell libraries reduces total power consumption by 41% and the die area by 11% (see table). As the die area is reduced, more chips fit on a wafer, and yield increases commensurately.
SRAM size is also reduced in the periphery, assuming that the bitcell area for bulk and SOI is the same. New concepts such as the floating-body embedded DRAM cell using only one SOI transistor are promising to significantly reduce the area of the memory array and may be used in a part of the memories of the chip.
Overall the cost of an SOI chip is not higher and may even be lower than bulk, depending on the application. SOI creates extra savings at the system level. With reduced power, heat generation is reduced, in turn reducing system cost. With SOI, the cell phone of the future can sizzle with style but stay cool to the touch.
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