For each technology node, those in the substrate world have to be ready with options years in advance of their customers. ASM describes developments in germanium epitaxy that could enable the industry to choose a GeOI future.
Soitec’s contribution has been to re-invent the silicon wafer through the development and production of SOI wafers. Most recently, “strained SOI” (sSOI) has been announced, developed in close collaboration with the ASM epitaxy and furnace product groups. sSOI will enable continuous performance improvement from the 45nm node onwards.
In addition to the Soitec “wafer scale” technologies, device and equipment makers have developed local strain processes using selective epitaxy of SiGe for PMOS and most recently also SiC for NMOS.
The Germanium Option
The combination of wafer-scale and local strain can be done up to the point where either the strain effect on the mobility “saturates” or where the strained epitaxial layers start to relax.
At that point, a new material for the channel region becomes unavoidable. The most obvious candidate is germanium because of its much higher mobility for both electrons and holes and because of its chemical similarity to silicon.
However, the worldwide availability of germanium-containing ores is very limited, ruling out a potential change to Ge wafers. To circumvent this limitation, ASM developed an innovative Ge on Si (GOS) process whereby only a thin epitaxial Ge layer is formed on a standard Si substrate.
GOS wafers are a natural starting material for Smart Cut™-based manufacturing of Ge on insulator on silicon substrates (GeOI) and can be supplied in any wafer size at much lower cost than Ge wafers. Such layers are now being evaluated not only for CMOS device manufacturing but also for optoelectronic applications.
Also of interest is the fact that Ge can be used as a lattice-matched substrate for GaAs, which has an even higher mobility than Ge. With such a substrate wafer, other III-V materials will become available to integrate unique electronic and optoelectronic capabilities on a Si wafer platform, enabling new device technologies while using cost-effective, large diameter wafers and state of the art production tools.
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