Strained Engineered Substrates: sSOI and Beyond
Posted date : Jul 11, 2006

The semiconductor industry has entered an exciting phase in which further performance gains (power, speed) are directly connected to materials engineering and the insertion of new materials into the heart of silicon integrated circuits.

The rate at which the industry is incorporating strain engineering into production is a direct result of using strained substrate materials in research and development for the requisite 10–15 years before such innovation can be incorporated into manufacturing.

From 1990 to 2002, prototypes of strained silicon devices with gate lengths larger than 90nm were fabricated from biaxial-strained silicon wafers to demonstrate the benefits of strained silicon technology. These materials allowed the community to reach a level of understanding about the benefits of strain as well as skirting deleterious issues that always accompany innovation.

Today, many strain effects are implemented at 90 nm and 65 nm technologies that allow devices to achieve drive currents that would be impossible if strain were not employed, thus allowing Moore’s Law to continue.

Process-Induced Limits

However, as with all technologies, strain has its limits. Current process-related implementations of strained silicon have boosted drive current somewhat but are insufficient to achieve future roadmap targets. Also, the most advanced implementations enhance PMOS more than NMOS. Can we see a path to higher NMOS and PMOS enhancements?

Based on the previous 15 years of strained silicon history, there are two pieces of information we can use to see into the future. The first is that substrate-based device prototypes at longer gate lengths accurately determine the potential of transport physics in channel-engineered materials.

The second is that research has defined the limits of current process-induced strain, and strain-engineered substrates will be required to further enhance transport through strain and the incorporation of new materials. Let’s consider these two factors in speculating which engineered substrates will be implemented over time.

Strain-sSOI Complement

Our research in strained SiGe MOSFET channels show that this materials system has the potential for increasing NMOS drive currents by a factor of 2 and PMOS currents by at least a factor of 10. Considering that the industry is motivated to change process to achieve increases today on the order of 10–30%, there is no question that the SiGe materials system is a premier target for engineered substrates.

But we must consider the drive to complement current process-induced strain and ease of inserting into current manufacturing processes. Combining these factors, a promising strain-engineered substrate is sSOI, or strained silicon on insulator.

There are many advantages to this strainengineered substrate configuration. The biaxial strain that pre-exists in this substrate material is large enough to boost electron drive currents by a factor of 2, much larger than today’s NMOS enhancements. Considering that the NMOS is also the lessenhanced transistor in today’s process-based strain, sSOI offers a natural complement to current strain engineered devices (strain effects are additive as the stress tensors in a material are additive). And in addition, the benefits of an SOI platform are also included in the engineered substrate.

Finally, the Smart Cut™ process incorporates the advantage of the SOI platform, but importantly it also removes the SiGe relaxed buffer material used to create the thin biaxialstrained channel. Thus, CMOS process integration is eased due to a lack of Ge present in the structure.

Further Ahead

Looking forward beyond sSOI, it is natural to ask whether strain-engineered substrates can also enhance the PMOS drive current, which would complement the enhanced NMOS (predominately through biaxial strain) and the enhanced PMOS (predominately through processes inserted in the CMOS process).

A dual channel structure on relaxed Si0.5 Ge0.5 on bulk Si. This structure has been shown to support 2x larger drive currents in NMOS at high inversion charge as well as a 10x in PMOS drive current. Both enhancements are with respect to control silicon MOSFETs. This channel can be implemented on an sSOI platform as shown in the schematic to achieve the ultimate strain engineered substrate.

Research shows that, given the band-offsets, effective masses, and device design in the strained SiGe system, biaxial strained SiGe incorporated into the substrate but beneath a thin silicon layer near the gate will be a logical progression from sSOI.

This materials platform also allows more flexibility for process-induced strain engineering. In addition, this “dual channel” structure can be incorporated directly on top of the sSOI platform, thus adding to a previously standardized generation of material.

The material platform can further evolve to enhance PMOS devices eventually to a >10x drive current by eliminating the silicon in the biaxial-strained SiGe layer. A real dual channel structure, which has demonstrated a 10x in PMOS drive current, is shown in the figure, as well as a schematic diagram showing the dual channel implemented on a sSOI structure.

The future of silicon technology lies in the combined efforts of substrate manufacturers and CMOS manufacturers. Working together, strain engineering can be partitioned across the substrate material and the process fab, resulting in an ever-increasing progression of drive currents in NMOS and PMOS transistors. Such technology can be used to increase transistor density and/or improve performance for a fixed gate length.

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