Strained Silicon-On-Insulator (sSOI) Becomes an Industrial Reality
Posted date : Jul 11, 2006

After several years of rigorous R&D work in close partnership with suppliers and customers alike, Soitec’s sSOI wafers are now ready for industrialization.

The benefits of strained silicon as an amplifier of carrier mobility, current drive and, as a result, device performance are well documented in literature and highlighted by Dr. Nguyen of Freescale in this same Advanced Substrate News issue. A strained silicon wafer platform was needed to assure the scalability of process-induced strain from the 45 nm technology node through the 32 nm node and further. Strained Silicon-On-Insulator (sSOI) is the answer.

sSOI is an evolutionary approach to SOI combining the advantages of SOI with the benefits of strained silicon. From the device perspective, it complements the processinduced stressor techniques. The device is engineered bottom-up from the substrate. The tensile strain in the NMOS regions is maximized during subsequent CMOS processing, while in the PMOS regions the tensile strain is first relaxed before introducing a compressive strain component along the channel. sSOI is a strain platform that allows the engineering of the appropriate tensile and compressive stress components along and across the channel independently for both transistor types.

sSOI is now ready to move into the 300 mm industrialization phase, the next ambitious phase of this program. Undoubtly, the development of sSOI has profited from the strong synergy with SOI, helping accelerate the development. But for a product based on the transfer of an epitaxial strained layer, the development of the silicon germanium template for the strained silicon layer growth and of the appropriate metrology became a crucial part.

Crystal quality learning curves

Figure 1: Crystal quality learning curves (A. Thean et al., VLSI 2006)

The development of sSOI and the establishment of a robust industrialization solution have been characterized by the strong partnership between equipment suppliers like ASM, SEZ, KLA-Tencor and OMI and by the strong coupling between device and substrate engineering with companies like Freescale.

At present, the tool set is defined, sampling and monitoring metrology identified and most important: sSOI product wafer is available. The main concern of the IC industry was the crystal quality of sSOI. Today’s sSOI quality has reassured the industry by eliminating killer defects like dislocation pile-ups and strongly reducing the dislocation density as shown in Figure 1. The current quality of this new substrate is compatible with complex IC fabrication.

With 500 wafer starts per month in 300 mm we assure sSOI availability to support device architecture development and continue on the rapid quality improvement of this new technology platform.

Stress wafer map of 2nd generation sSOI

Figure 2: Stress wafer map of 2nd generation sSOI, exhibiting a 2.5GPa mean value.

sSOI is fully compatible with partially and fully depleted device architectures, and has been proven for FinFETs and Multi Gate FETs. sSOI as a template for subsequent epitaxy opens the door to band gap engineering in combination with Ge or SiGe germaniumrich epitaxy. Also known as “dual channel”, the technique has been shown to lead to the highest hole mobility values achieved for a PMOS. sSOI built-in stress averages 1.4GPa. Its scalability to 2.5GPa has been demonstrated, enabling further performance enhancement (Figure 2).

In summary, sSOI offers the industry a powerful, high-mobility platform today.

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