Harnessing SOI’s Floating Body Effect for Dense Memory Cells
Posted date : Dec 6, 2006

The co-inventor of Z-RAM explains the technology.

As a Z-RAM – zero capacitor RAM – memory technology bit cell uses only a transistor plus the floating body effect inherent in SOI processing (see Figure 1), it typically measures only 15-20F² (where F is the technology minimum feature size).

Compared with SRAM (where the six transistor bit cell measures around 150 F²), or embedded DRAM (which requires a capacitor for a bit cell size of 30-40F²), the density advantages of Z-RAM are obvious.

When Z-RAM replaces eDRAM, silicon estate is halved; when used to replace SRAM, the space savings are 80%. It uses standard SOI logic processes without new materials, extra process or masking steps. The savings can be leveraged to either massively reduce cost or to include more functions on the chip.

Speed, Power or Density

The key drivers for electronic circuitry are density, speed and power. As Figure 2 shows,
Z-RAM can be optimized for any of these three parameters.

As speed is dependent mainly on the capacitance of the bit line, for fast access times the bit line can be shortened to deliver up to 400MHz array speed at 65nm. For low power operation, although a shorter bit line does reduce power the effect is not that great since the change in bit line voltage is small. However, by reducing the Word Line length and hence the Word Line capacitance, active power levels of only 10Wµ/MHz at 65nm are achievable.

To achieve the ultimate in array density (>5Mbit/mm²), longer Word Lines and Bit Lines are required. However this is obviously at the expense of access time and power.

Z-RAM memory technology was co-invented by Pierre Fazan and Serguei Okhonin, who also co-founded Innovative Silicon Inc. (ISi) to commercialize the technology.

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