From the IEEE ’06 SOI Conference:
“Best Paper” indicates RF on thin HR SOI can open the door to low-cost, mass-market 200GHz applications in the coming year.
A paper presented by STMicroelectronics in conjunction with IMEP UMR and IEMN, entitled “State of the art 200 GHz passive components and circuits integrated in advanced thin SOI CMOS technology on High Resistivity substrate” (F. Gianesello et al) won Best Paper Award at the IEEE 2006 SOI Conference. The paper concluded that HR SOI can be used in the coming year to open up the V, W and G bands (up to at least 200GHz) – previously the domain of expensive III-V technologies – to low-cost, mass-market CMOS digital and RF/MMW applications. (Proceedings, p.121)
FD-SOI for ultra-low power digital and RF.
Stressing the importance of expanding fully depleted (FD) SOI devices for ultra-low power digital analog and RF applications (integrating MEMS/sensors, for example), researchers from Oki Electric presented major characteristics and issues of FD-SOI, and proposed new device structures and processes for near-term solutions. (Proceedings, p. 15)
Leveraging the SOI floating-body effect to improve electrostatic discharge- related reliability at 65nm.
IBM and AMD leveraged the floating body (FB) effect in SOI to design I/O circuits with improved ESD characteristics. The results offer the designer a wider window and greater flexibility at 65nm and beyond. (Proceedings, p.38)
Effects of temperature on metal gate FinFET circuit performance.
A paper from Texas Instruments, ATDF, Infineon and Soitec shows the promise of fully depleted FinFETs for high-temperature operation in digital, analog and mixed signal design. Potential applications include chips used close to an automotive engine block or in oil drilling. The paper demonstrates the advantage of FinFET circuits with performance of analog and digital building blocks from –50ºC up to 300ºC, a range that would be very difficult to attain in bulk.
From ECS 2006, the 210th Meeting of The Electrochemical Society:
A special Workshop was devoted to the prospects of CMOS in germanium. Speakers represented IMEC, CEA-LETI, IBM, Stanford, and MIRAI/University of Tokyo. Since Ge is expensive, heavy, and fragile, any practical implementation would be in the form of GeOI wafers. However, much progress is needed – currently PMOS in Ge is feasible, although very short devices still need to be convincingly demonstrated. There has not been any success yet in building NMOS devices in GeOI. Some groups propose integration of Ge-PMOS with Si (or GaAs) NMOS. (Abstracts 1480-1484)
Fabrication of hybrid Si substrates by Direct Silicon Bonding (DSB).
A paper presented by Soitec and CEA-Leti detailed a Smart Cut™ enabled process for fabricating directly bonded 300mm silicon substrates with hybrid crystal orientation for use in advanced bulk CMOS technology. (Abstract #1241)
Extra-Strained Silicon-On-Insulator (XsSOI) development.
Researchers at Soitec and CEA-Leti detailed the development of 300mm bi-axially highly-strained Silicon-On-Insulator (sSOI) substrates with up to 2.5 GPa tensile stress level by using SiGe with up to 40% Ge content in the donor wafers and Smart Cut™ technology. (Abstract #1358)
Hydrogen implant induced strain depends on crystallographic orientation of silicon.
Researchers from the CEA, Leti and Soitec presented an x-ray scattering study investigating the effect of hydrogen implantation in silicon single crystals with (100), (110) and (111) orientations. They showed that the strain level varies with the crystalline orientation and that the strain profile corresponds to the distribution of the hydrogen atoms in the implanted target, rather than to recoil defects. (Abstract #1359)
Effectiveness of embedded-SiGe in SC Strained-SOI.
AMD and Soitec found that the drive current improvement from embedded-SiGe is equal if not more for super-critically thick sSOI than for standard SOI. Uniaxial stress generated by the embedded-SiGe was found fully effective on sSOI. The research also indicated that vertical lattice mismatch is the dominant mechanism for channel stress generation from embedded-SiGe. (Abstract #1474)
Optimizing performance through a combination of wafer-level and process-induced stress.
Building on work from Leti, ASM and Freescale, Soitec researchers explained how to combine process-induced stress and wafer-level stress to obtain the optimum transistor performance gain. They presented the main characteristics of highly strained sSOI (up to 2 and 2.5Gpa) including typical morphological data (thickness, crystal defectivity and the very first electrical data), and demonstrated a clear path towards further increasing sSOI built-in stress. (Abstract #1444)
New generation of structures obtained by direct wafer bonding of processed wafers.
TRACIT Technologies described new wafer bonding technology for IC or MEMS manufacturing, enabling processed layers to be stacked or transferred to another support, while maintaining their quality and characteristics. (Abstract #1355)
SOI material readiness for 45nm and Sub-45nm device options.
Soitec outlined the availability and readiness of SOI substrates for PD and FD device architectures, including layer total thickness variation of ±1 nm, changes in crystalline orientation and the dramatic increase in the quality of sSOI due to improvements in strained silicon epitaxy. (Abstract #1240)
Improved SiGe crystal quality and elimination of dislocation pile-ups using automated room-temperature photoluminescence mapping.
Accent Optical Technologies and Soitec demonstrated the use of automated, room temperature photoluminescence (RT-PL) as a guide to process development for modern biaxial strained Si/SiGe materials (as in strained SOI). Advances in image acquisition and processing enable dislocation pile-up (DPU) quantification, assessment, and mapping over entire wafers. This contributed to significant reductions in process development cycle times required to produce high quality SiGe-based materials. Crystal quality was improved, misfit dislocation (MD) crosshatch effects identified, and DPUs eliminated in SiGe deposited films to the limit of detection. (Abstract #1507)
Ge diffusion in strained Si / relaxed SiGe heterostrucutures
To improve hole mobility in PMOS with substrate-level strain alone, it is necessary to increase the biaxial strain to about 1.5% (stress of 2.5-3 GPa) in “globally strained” sSOI wafers. Relaxed layers of SiGe with 40% Ge need to be grown as virtual substrates for strained Si epitaxy. Such highly strained films have been demonstrated but significant optimization is still required to reduce defect densities. In this paper, CEA-Leti and Soitec studied the Ge diffusion in highly strained silicon (sSi) layers deposited on SiGe virtual substrates. They used two Ge concentrations (30 and 40%, corresponding to a 1.8 and 2.5 GPa strain level respectively; current sSOI wafers use about 20%) to induce strain in the Si layers. (Abstract #1511)
Compound materials bonding and layer transfer for optoelectronic applications.
Soitec gave an overview of engineered substrates for optoelectronic applications, focusing on layer transfer of GaAs, InP, SiC and GaN. (Abstract #1382)
High carbon content channels for FD-SOI nMOSFETS.
Researchers at CEA-Leti used reduced pressure CVD to grow high quality Si1-yCy layers for use as the channel for n-type FD-SOI devices with TiN metal gates. They demonstrated the interest of using Si1-yCy to adjust the threshold voltage of n-type FD-SOI with midgap metal gate by varying the carbon concentration in the channel (which is a similar effect to using a strained SiGe channel in p-type MOSFETs).
GaN Epitaxy by MBE on Silicon and Engineered Substrates.
Picogiga presented MBE developments in GaN on silicon that lower defect density and change the nature of defects. The researchers also presented promising Smart Cut™ enabled engineered substrates that could replace silicon for high power amplifiers or low noise applications. (Abstract #1310)
SOI-based CMOS photonics for high-speed interconnects.
Luxtera presented optical transceiver cores operating at 10Gbps, enabling high-speed optical communications directly between silicon die at a price/performance point superior to traditional electrical interconnect. The transceivers are monolithically fabricated alongside SOI CMOS circuitry in the same die, containing 10s of optical components and 100,000s of transistors. (Abstract #1394)
In ECS Interface, Winter 2006 issue:
Advanced Electronic Substrates for the Nanotechnology Era.
Soitec presents a review of engineered substrates that are needed for current and future device generations. The paper covers state-of-the art conventional SOI, high resistivity SOI, strained SOI, GeOI, SOI with alternative buried dielectric layers, and a variety of unique applications that are enabled by these advanced substrates.
From the 16th International Conference on Ion Implantation Technology:
Time Dependence Study Of Hydrogen-Induced Defects In Silicon During Thermal Anneals.
Soitec’s patented Smart Cut™ technology, which is the primary means of creating SOI wafers, is based on ion implantation and wafer bonding. When hydrogen is used for ion implantation, a large variety of H-related defects, including platelets are created. Thermal annealing is one of the possible technological options to obtain the layer transfer of thin films in Smart Cut™ technology. Annealing induces the formation of large gas-filled micro-cracks in the implanted Si, so the wafer splits precisely at the hydrogen-implanted zone. However, many physical aspects of implanted H evolution are still unclear. In this paper, Soitec researchers present a time-dependence study of the evolution of hydrogen-induced defects in Si after isothermal treatment. They calculated the kinetics of H2 formation, and showed that the splitting is determined by H migration and rearrangement of hydrogenated defects. Further studies are in progress to identify the thermo-mechanical phenomena occurring at the later stages of microcrack formation and interactions.
From the European Materials Research Society Spring (2006) Meeting:
Hydrogen implantation-induced defects in bulk Si studied by Raman spectrometry.
Ion implantation is widely used in the semiconductor industry to modify the carrier density in a transistor channel region, and to enable splitting in the wafer bonding process. In the case of SOI wafers produced by Smart Cut™ technology, the implantation of light ions, creates only a small amount of damage in the materials. Thus, H-implanted Si remains crystalline and only small changes are observed in physical properties as compared to non-implanted silicon crystal. However, as energy is applied to the system, by heating for example, H-implanted Si undergoes extreme stress eventually breaking the crystal. In this paper, Soitec researchers present the results of an investigation into the changes in the Si crystal during this process using Raman spectroscopy.
Published in the New Journal of Physics, 8 (2006):
Electrical conductivity in silicon nanomembranes.
SOI serves as the foundation of a nascent nanotechnology: Si nanomembranes (SiNMs), which are extremely flexible and maintain their perfect-single-crystal, dislocation-free nature. Because of their thinness, their shape, and the strain that is introduced via heteroepitaxy, they can have unique properties. This paper by a team from the University of Wisconsin-Madison and Soitec describes surprising electronic conductivity in very thin SiNMs in terms of a ‘surface doping’ mechanism.
From the 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT)
sSOI Technology for High-Performance CMOSFETs in 45nm-or-below technology node.
Researchers from Soitec presented a paper outlining the status and future of strained SOI technology for high-performance ICs. Smart Cut™ enables the transfer of a tensile-strained Si film onto a 300mm Si wafer, with excellent thickness uniformity and preserved stress. The pile-ups (PUs) have been eliminated and the threading dislocation density has been significantly reduced. Strained-Si film can be 80nm thick, making implementation of partially-depleted (PD) structure practical. The stress endures thermal treatment up to 1100 degree C, for 2 hours. Technology directions for PMOS improvement are discussed, including combination with uniaxial stress technologies.
From the Journal of Materials Science Forum (Vols. 527-529):
Processing of Poly-SiC Substrates with Large Grains for Wafer-Bonding.
A new generation of engineered wafers based on pSiC is promising for compound semiconductors such as GaN HEMTs. However, CMP is challenging. A paper by researchers at the CNRS, INSA-LPM, NOVASiC and Soitec presents optimized polishing to obtain low surface roughness.
From the Journal of IEEE Electron Device Letters:
Impact of sSOI Substrate on FinFET Mobility.
Texas Instruments, Infineon, ATDF, Soitec, UC Berkeley and Synopsys show that for fin widths down to <20nm, strain can be retained in patterned sSOI films and is correlated to mobility enhancements observed in FinFET devices. NMOS FinFET mobility is improved by 60% and 30% for (110)/<110> and (100)/<100> fin surface/direction, respectively. Although PMOS FinFET mobility is degraded by 35% for (110)/<110> fins, it is enhanced by up to 30% for (100)/<100> fins. These results can be qualitatively explained using the bulk-Si piezoresistance coefficients. (July 2006)
Room-temperature low-dimensional effects in Pi-Gate SOI MOSFETs.
UC Davis, Texas Instruments, Infineon and Soitec find evidence of a one-dimensional subband formation in Pi-gate SOI MOSFETs at room temperature as oscillations are found in the ID(VG) characteristics. These oscillations correspond to an intersubband scattering. Even though the height-to-width ratio of the silicon fins is equal to five, the device behavior is better described by a one-dimensional semiconductor theory than by a two-dimensional gas model. (September 2006)
From the Device Research Conference:
FinFET performance enhancement with tensile metal gates and strained silicon on insulator (sSOI) substrate.
Texas Instruments, Soitec, UC Berkeley and Synopsys report on FinFETs with highly tensile (3GPa) metal gate electrodes. 100% improvement in (110) electron mobility is achieved while retaining high (110) hole mobility, for FinFETs fabricated on SOI substrates. Even greater improvement in electron mobility is seen when a tensile gate is used in conjunction with an sSOI substrate, so that the (110) electron mobility exceeds that of the (100) universal mobility curve by 20%.
From the IEEE Nuclear and Space Radiation Conference:
Radiation Dose Effects on Tri-Gate SOI MOS Transistors.
UC Davis, Texas Instruments, Infineon and Soitec describe the results of irradiation of trigate SOI transistors with doses up to 6 Mrad(SiO2). The devices show high resistance to dose irradiation. An increase of transconductance is observed for moderate dose irradiation.
From ESSDERC 2006:
Self-Heating Simulation of Multi-Gate FETs.
Due to material properties and geometric aspects, self-heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. Work by Infineon, Texas Instruments, ATDF, Soitec and UC Davis demonstrates a simplification so that time constants and thermal capacitances for thermal compact models, which are usually difficult to extract experimentally, can be simulated numerically.
From ESSCIRC 2006:
Multi-gate MOSFET Design.
Infineon, Texas Instruments, Soitec and ATDF discuss circuit design issues of emerging multi¬gate field effect transistors (MuGFET) with special emphasis on the link between circuit design and technology. The influence of novel midgap gate electrode materials on digital circuits is presented and examples of the first basic analog building blocks realized with these advanced devices are shown. Furthermore the influence of new device-specific effects on analog circuits, like self heating or output conductance improvement due to undoped body are discussed and RF and ESD issues are covered.