Starting with SOI wafers, Professor Lagally’s team has developed strain-engineered silicon nanomembranes that could pave the way to flexible, high-speed circuits and more.
SOI, beyond its well-known use in CMOS devices, provides the foundation for a new class of structures: strain engineered Si nanomembranes. These membranes offer the promise for new devices or increased performance in applications as diverse as high-speed flexible electronics, light detection and imaging, piezoresistive devices, nanoelectromechanical-systems (NEMS) and other nanosensors, and potentially light emission.
Membranes offer flexibility, light weight, easy integration with many other materials, and possibly higher device densities. The strain offers higher CMOS device speeds and controllable modification of the band structure. These features enable new directions for the use of Si in electronics, photonics, and thermoelectrics, and the integration of Si with magnetic and ferroic materials.
The ability to etch the buried oxide in SOI selectively creates thin single-crystal sheets of silicon that are quite flexible and transferable to any number of other hosts. More importantly, by heteroepitaxial growth of Ge alloy on the SOI before oxide etching to release the membrane, uniform lattice strain can be introduced without the creation of dislocations.
A simple example of an elastically strained Si nanomembrane is a Si/SiGe/Si sandwich, in which the SiGe alloy strains the Si layers. Tensile strains of 0.4% are readily obtained in a 3-layer membrane that is 200nm thick. Such strains significantly raise the electron mobility.
All conventional Si processing is possible in such membranes. Because the membranes are flexible, transferable, and readily bondable to new hosts, they form the basis of very fast flexible electronics. Figure 1 shows thin-film transistors (TFTs) fabricated in a strained Si/SiGe/Si membrane and an image of a sheet of TFTs transferred to plastic. Because a Si/SiGe/Si membrane has two free Si surfaces, fabrication of devices on both sides is possible using simple membrane transfer processes.
As a second example, Si nanomembranes may have a potentially high impact in photodetectors with improved speed or resolution. By integrating Si and Ge alloy nanomembranes in thin multilayer structures, we can fabricate PIN diodes, either on solid SOI or transferred to flexible substrates, in which the intrinsic layer is Ge or SiGe and the p-type and n-type layers are Si.
Membrane structures with higher degrees of complexity are possible, using known epitaxial growth techniques. Membranes can also be fabricated into various shapes using appropriate strain engineering. We expect that Si nanomembranes, based on SOI or variants of SOI, will form a technology platform that will enable many new semiconductor devices or improvements in current ones.
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