Leti lab director and inventor of the principle of contact plugs now leveraging advanced substrates.
In further recognition of his distinguished career, Dr. Simon Deleonibus, Director of Leti’s Electronic Nanodevices Laboratory, was recently awarded the grade of IEEE Fellow “for contributions to nanoscaled CMOS devices technology”. This follows on other recent awards including the Grand Prize of the French Academy of Technologies and the Knight of the National Order of Merit by the French Presidency.
The author of over 300 papers and holder of 28 patents, he is well known as the inventor of the principle of contact plugs, now used in integrated circuits worldwide.
He and his Leti team leveraged SOI in 1999 when they set the world record for smallest transistor, with a 20nm gate length and 4nm channel length.
Today, he is an enthusiastic advocate of advanced substrates. “The great majority of our devices architectures from 65nm down to sub-22nm are achieved on SOI or other related engineered substrates,” he says. “SOI gives you enormous flexibility in designing new devices architectures. Double-gate CMOS, FinFETs, FD and PD devices: we’ve pushed them down to sub-10nm gate lengths (5nm range channel lengths).”
SOI and other engineered substrates leveraging a wide range of materials and technologies, he speculates, may well be the Holy Grail in the eternal quest for low-power, high-performance applications.
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