Thin BOX: A Solution for High-Speed, Low-Power SoCs
Posted date : Dec 6, 2006

Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond.

Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node.

Figure 1. A schematic cross-sectional view of “Silicon on Thin BOX”. By reducing the BOX layer to 10nm, the Si substrate can be used as the second gate (back gate).

Hitachi and Renesas are developing a novel structure, “Silicon on Thin BOX”, where the buried oxide (BOX) is approximately 10nm thick, enabling the control of MOSFET characteristics by biasing the Si substrate [Ref]. “Silicon on Thin BOX” is expected to provide a solution for simultaneously achieving high-speed and low-power at the 45nm technology node and beyond.

Si substrate as back gate

Figure 1 shows the “Silicon on Thin BOX” structure, with a BOX film of 10nm. As a result, the Si substrate (the “handle” or “mechanical support” of the SOI wafer) can be used as the second gate (back gate), achieving a 20% increase in the operation current. Stand-by leakage is reduced by over 90% — more than one order of magnitude.

Figure 2. Threshold voltage (Vth) control in a “Silicon on Thin BOX” structure. Multiple threshold voltages becomes possible through the work-function of the NiSi gate electrode, as well as impurity doping underneath the BOX layer by varying the doping level.

In the actual structure, multiple threshold voltages becomes available, by work-function control through the fully-silicided metal gate structure (FUSI) using NiSi, as well as impurity-doping underneath a BOX layer, as shown in Figure 2. Moreover, unlike bulk Si devices, there is no need for doping in the channel region to suppress the short channel effect. This eliminates the scattering of threshold voltage caused by the statistical fluctuation of impurity atoms, which is known to become a dominant mechanism in a short channel region. This is expected to contribute to the lowering of the minimum operation voltage, enabling further power reduction.

[Ref.] R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, “Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control,” IEDM 2004 Tech. Dig.,
pp. 631-634, (2004).

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