As we approach the end of the roadmap, single gate FD SOI devices with ultra-thin BOX could pre-empt the need for double gate devices.
It is well known that UTB (Ultra Thin Body) devices present improved electrostatic integrity. We were, however, among the first to report  on the importance of the BOX thickness with respect to the electrostatic integrity of SOI devices. The electrostatics of FD SOI devices (we’ll focus on DIBL — Drain Induced Barrier Lowering – a widely used figure of merit for MOSFETs) can be captured within the following simple equation :
It confirms that with SOI, DIBL reduces not only with thinner top Silicon Film (Tsi), but also with thinner BOX.
The practical question then arises: how thin should the BOX be? As shown in Figure 1, thinning the BOX from 150nm down to roughly 50nm is not very productive since the curve remains more or less flat. In contrast, beyond 40nm the curve drops down and the gain in DIBL is becoming significant.
For the BOX thickness of 10nm, as much as a 50% reduction in DIBL can be expected. Beyond 10nm, as we have shown , the speed of the device starts to deteriorate due to an enhanced coupling with the substrate via the thin BOX. Therefore, 20nm BOX seems to be a good and secure compromise.
The effect of BOX thickness is less than that of silicon thickness. Nevertheless, the use of ultra-thin BOX enables us to approach the electrostatics of Double Gate devices, while still remaining within the Single Gate scheme. CMOS integration on Ultra Thin Body & BOX SOI (we call it UTB2) may be technologically much simpler than any known Double Gate technology, and thus may be a battle horse for end-of-the-roadmap CMOS.
1. T. Skotnicki et al., ECS 2003 Paris, ULSI Process Integration III pp.503-518 & SOI Technology and Devices XI pp. 133-148
2. T. Skotnicki et al., MASTAR Guide and Software via the metalink in the 2005 edition of ITRS (http://www.itrs.net/models.html)
3. T. Skotnicki, 2004 Symp. On VLSI Technology, Short Course Proceedings.
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