UT BOX SOI: Engineering for Future Low-Power Applications
Posted date : Dec 6, 2006

Ultra-thin buried oxide may solve some key design challenges at 32nm.

Leading-edge microprocessors built on SOI have maximized performance while respecting the power budget by decoupling the Si surface from the substrate with a 150nm-thick buried oxide (BOX).

However, moving towards low-power, high- or mid-performance CMOS applications, an increased coupling between the top layer of silicon and the handle substrate becomes paradoxically interesting. Reducing the BOX thickness provides several benefits.

For example, fully depleted (FD) IC architecture is highly suited for low power design, but is not compatible with a multi-threshold voltage (multi VT) design. Taking advantage of a back gate bias through the substrate will set the VT at different levels throughout the circuit without high dose implants, which are technically difficult for FD devices.

Furthermore, the designer will be able to work with the substrate doping without additional implants, thus maximizing carrier mobility, eliminating VT mismatch due to dopant fluctuation in implanted channels and reducing short channel effects. All this while assuring the Ion/Ioff ratio > 106.

The BOX thickness required to assure sufficient back gate control at VDD<1V without the need for area-consuming charge pumps is in the range between 10 to 25nm. Thus ultra-thin BOX (UT-BOX) will have to guarantee an oxide integrity comparable to that of gate oxides.

At present the development of UT BOX SOI substrates is mainly driven by floating body cell DRAM and FD MOSFET applications. However, UT-BOX SOI CMOS constitutes a serious challenger for FinFET devices at the 32nm technology node.

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