High-k and Metal Gates Pave the Way to Further Innovation
Posted date : May 11, 2007

Here’s why HK+MG+SOI promises to be a winning combination.

Seen as a necessary innovation to assure the IC scaling path, high-k gate dielectrics combined with metal gates have been in development for more than a decade. Recent announcements by IC technology leaders highlight the transition from R&D to early manufacturing for high-k and metal gate modules. It is an innovation that will benefit the IC industry as a whole and will open the path to further improvements.

In particular, the choice of fully-depleted (FD) SOI with high-k and metal gate architecture offers many more advantages compared to its bulk counterpart. In a FD transistor, the channel doping can be eliminated, thus reducing to a minimum channel dopant dependent threshold voltage Vt variability without degrading short channel behavior.

Further, the metal gate process can be simplified to a mid-gap metal gate. The reduction of Vt scatter translates into a much more stable SRAM cell, which is otherwise a serious issue for the 45nm technology node Si bulk based FETs.

Higher mobility, lower power

Another significant advantage of an undoped channel is a 30% better mobility than its Si bulk counterparts, which in turn amplifies the strain-induced mobility enhancement via local stressors and at the wafer level.

In dynamic operation the reduction in parasitic vertical and lateral capacitances improves the frequency responses for a given voltage supply, which weigh heavily in channel implanted FETs. This in turn translates into significant dynamic power savings at the circuit level. Furthermore, due to its SOI nature the FD device exhibits a very low leakage even at 125°C, thus also significantly lowering static power consumption by at least an order of magnitude.

With ultra-thin SOI

For FD devices, the device Vt dependence on SOI Si thickness uniformity has been considered for a long time as the main hurdle for the implementation of this FET architecture. Smart Cut™ technology development has made possible today a thickness controllability in high volume for the initial top Si better than 10Å, ±3 sigma, which eliminates the SOI substrate induced variability of the FD device parameters.

Future innovations that will enable the scaling path beyond 32nm are 3D devices like multi-gate FETs and FinFETs. Published results from different industrial R&D teams have shown that high-k / metal gates are very beneficial to these devices. Also in development are new materials with intrinsic high mobility for after the 22nm node like III-V and Ge-on-insulator FETs, which have been shown to be specially suited for high-k / metal gates.

Development work at Léti/CEA and Soitec focusing on the integration of high-k dielectrics with mid-gap metal gates coupled to the development of ultra-thin SOI has yielded robust fully depleted FETs down to the 30nm gate length. These leading edge results and the progress achieved by the Léti FD SOI teams have been reported in recent IEDM and VLSI conferences, and other symposia.

Figure 1. TEM cross section of a 25nm FDSOI transistor. Film thickness is 8nm. Gate stack is: 3nm HfO2 + 10nm PVD TiN + 50nm poly-Si. (Courtesy: CEA-Léti, STMicroelectronics, Freescale Semiconductor. “Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate stack for FDSOI cMOSFETS down to 25nm Gate Length and Width,” F. Andrieu et al. IEDM/Electron Devices Meeting 2006, pp. 1-4, Dec. 2006)

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