Here’s why ARM, the industry’s leading provider of intellectual property for processor, peripheral and SoC design, sees SOI technology as a powerful tool in the quest for optimized performance and power consumption.
Silicon-On-Insulator (SOI) technology offers designers an opportunity for product differentiation and value creation.
Adopting well-designed SOI physical IP products gives ASIC designers additional choices in how they approach higher performance and lower power in a broad range of applications, including mobile, home, enterprise and embedded markets. SOI-enabled choices can help designers create value by differentiating their products and reducing system costs.
However in order for SOI technology to expand beyond full custom-designed chips into the mainstream ASIC market, the design community needed a viable design environment. To that end, ARM has developed physical IP products – standard cell and I/O libraries and SRAM memory compilers.
The ASIC designer who chooses to license ARM® IP can enable close timing and accurately predict the performance of any SOI ASIC without having to understand the underlying device physics.
In characterizing the IP, ARM covers the SOI-specific issues. This proprietary characterization methodology avoids both oversized margins and design risk.
Whether the model is fabless, fab-lite or IDM, this considerably reduces the ASIC designer’s task. And, it ensures that the non-recurring engineering (NRE) cost of adopting the ARM SOI IP for any ASIC project is minimal and requires little or no change to EDA flows.
ARM sees intrinsic benefits in SOI technology for alternative optimizations of what ARM refers to as PPA: power, performance and area. In particular, SOI provides opportunities for designers of:
• Mobile applications: where battery life is at a premium, and/or where RF device integration is advantageous.
• Consumer electronics: for applications processors requiring higher performance, smaller form factors, and savings incurred in packaging and heat management.
• Embedded markets: where the emphasis is on performance, size, power and reliability (especially under challenging conditions as found in automotive, industrial, medical and appliance markets).
Even in certain ASICs that will not be scaled further, switching at the same technology node from bulk to SOI can improve PPA, thereby providing additional product differentiation choices.
Studies indicate that the overall cost of using SOI rather than bulk silicon can be neutral and may even be lower, depending on the application1
From the designer’s standpoint, the SOI design flow is virtually the same as for bulk.
ARM’s physical IP is modeled from SOI-specific spice models. As the designer generates netlists and optimizes placement and routing, the SOI-enabled physical IP is transparently integrated into the IP views. The procedures are standard and compatible with existing ASIC EDA design tools.
The layout takes advantage of the SOI specific design rules to shrink the cell to the minimum, which typically saves 10 to 20% of silicon area compared to similar bulk CMOS implementations.
The only effect SOI IP has on the ASIC flow is that an additional static timing analysis (STA) corner is required to map the history effect. SOC level timing closure tools are now on-chip-variation (OCV) and multi-corner aware during place-and-route optimization, thereby extracting the maximum performance available from the technology.