IBM researchers have made strategic advances in key elements needed to achieve on-chip optical networks.
The current trend in the microelectronics industry is to increase the parallelism in computation by multi-threading, by building large-scale multichip systems and, more recently, by increasing the number of cores on a single chip. With such an increase of parallelization the interconnect bandwidth between the racks, chips or different cores is becoming a limiting factor for the design of high performance computer systems. In particular, massively parallel processing within a multi-core architecture is becoming limited by large power consumption and limited throughput of global electrical interconnects.
To address this issue, the on-chip ultrahigh-bandwidth silicon-based photonic network might provide an attractive solution to this bandwidth bottleneck. Miniaturization of silicon photonic devices is a key towards practical realization of these ideas.
Silicon-on-insulator (SOI) technology is ideal for building ultra-dense photonic devices and circuits for an on-chip optical network.
Good optical isolation provided by the micron-thick buried oxide layer (BOX) allows one to shrink the core size of silicon waveguides to submicron cross-sections.
Simultaneously, owing to strong light confinement within a waveguide core, such waveguides, often called photonic wires, can route optical signals over very sharp corners with bending radii as small as just a few microns.
Recently IBM Research has demonstrated that this SOI-based technology opens the way to aggressively scale the footprint of all photonic components required for complex on-chip optical networks down to just a small fraction of a square millimeter. As it is typical in scaled CMOS devices, the power consumption of such devices is also dramatically reduced to sub-milliwatt levels.
Among recent IBM Research demonstrations are:
At this level of miniaturization the size of optical components is becoming comparable to the footprint of CMOS devices, suggesting the way towards monolithic integration of advanced CMOS circuits and nanophotonic optical components at the CMOS front-end.
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