ST reports on highly integrated SRAM and RF on 300mm wafers. Yield matches bulk with improved FOM.
Wireless communications systems may soon replace personal computers as a key driver of volume manufacturing.
A full CMOS 65nm Partially Depleted Low Power (LP) SOI technology has been developed at STMicroelectronics on high resistivity (HR) (› 1kOhm-cm) 300mm SOI wafers provided by Soitec. This latest work is the first to prove that 300mm HR SOI can match bulk yield, with improved figures of merit (FOM) of both digital and RF circuits, for high-volume wireless applications
This HR SOI substrate helps increase the integration of passive components by area saving for given quality factors, without a very thick copper back-end process. The functional RF circuits are state of the art with low noise and high gain, even in the very high frequency range.
An HR substrate can’t be used on bulk due to latch-up. With low resistivity substrates, parasitic capacitances and the attenuation constant of propagation lines degrade high-frequency performance, especially for mm-wave circuits above 60GHz.
Limited battery life makes power dissipation the main issue for wireless portable systems.
Compared to a similar design in bulk, the 65nm HR SOI on 300mm wafers gave us:
Thin SOI advanced technologies with a high resistivity substrate are consequently very good candidates to integrate RF and digital circuits in the same chip, as RF performance as well as a lower power and higher speed can be reached with a full standard SOI CMOS process.
References: “80 GHz Low Noise Amplifiers in 65nm CMOS SOI”, Baudouin Martineau et al, ESSCIRC 2007 “Integrated Inductors in HR SOI CMOS technologies: on the economic advantage of SOI technologies for the integration of RF applications”, Frederic Gianesello et al, IEEE Int. SOI Conference 2007.
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