With scaling, SRAM design rules are far tighter than logic. New device structures may be needed.
6T SRAMs are the backbone of embedded CMOS memory. Today SRAMs occupy over 50% of the total chip area. The SRAM cell sizes have been shrinking by ~50% each node. Such aggressive scaling has pushed SRAM design rules far tighter than logic.
Major FEOL challenges facing 6T SRAM at 32nm and beyond are:
Scaling degrades all three parameters. High local variation undermines SRAM stability; low Iread slows the access time; while poor isolation increases leakage.
A major source of transistor local variation is Random Dopant Fluctuation (RDF). RDF can be reduced by the use of high-K and metal gate. However, even with such advanced gate stacks, the 50% scaling trend may not be sustained beyond the 32nm node.
New device structures, such as Multi-Gate MOSFETs (MuGFET) maybe needed for future 6T SRAMs. MuGFETs can reduce RDF by 4X (see Figure 1). Such drastic improvement is the result of undoped channels and metal gate.
MuGFETs also improve Iread by converting the transistor width from wafer surface to the vertical “fin” sidewalls. Therefore, Idrive can be increased by taller fins without affecting the cell footprint.
A natural implementation of MuGFETs is on SOI substrates. SOI substrate also eliminates the transistor isolation problem. MuGFETs can be fabricated on bulk wafers with additional processes and variations.
In addition to FEOL challenges, contact and BEOL design rules are also pushed to the limit. A prime example is contact-to-gate spacing. At worst-case misalignment, this spacing approaches the gate oxide thicknesses of earlier nodes. Thus, contact-to-gate reliability is an important issue.
Aforementioned challenges will likely slow down 6T SRAM scaling. In order to satisfy the everincreasing demand for embedded memories, novel high-density cell structures, such as floating body cell (FBC), maybe needed to continue the historical scaling trend.
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