Conference Proceedings
Posted date : May 14, 2008

Materials Research Society (MRS), Spring Meeting 2008, San Francisco.

Formation of III-V semiconductor engineered substrates using Smart CutTM layer transfer technology. Fabrice Letertre (Soitec).

This paper reviews the current wafer bonding and layer transfer technologies with a special emphasis on the Smart CutTM technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering is illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/optoelectronics functions hybrid integration. Recent results obtained in these two focused areas are presented to emphasize the added functionalities offered by engineered substrates.

Growth of AlGaN/GaN HEMTs on Silicon Substrates. Fabrice Semond, Yvon Cordier, Nicolas Baron, Sylvain Joblot, Eric Frayssinet, Jean-Christophe Moreno and Jean Massies (CRHEA-CNRS, Picogiga, and STMicroelectronics).

AlGaN/GaN high electron mobility transistors (HEMTs) are of great interest due to their capabilities to work at high temperature and to achieve high output power densities. For these reasons they are expected to be used for next-generation of power amplifiers. This paper gives an overview of what has been achieved in the field of AlGaN/GaN HEMTs on Si substrates and discusses why it has been so successful to grow on Si. Recent developments as well as the latest state of the art AlGaN/GaN heterostructures grown on silicon substrates are presented.

Direct Growth of III-V Devices on Silicon. Katherine J Herrick, Jeffrey Laroche, Thomas E. Kazior, Amy W. K. Liu, Miguel Urteaga, Berinder Brar, Mayank T. Bulsara, Eugene A. Fitzgerald, David Clark, Nicolas Daval, George K. Celler (Raytheon, IQE, Teledyne, MIT and Soitec).

The starting material is based on a unique silicon template wafer invented at MIT and fabricated by Soitec. These silicon-on-lattice-engineered substrates (SOLES) contain an embedded compound semiconductor (CS) template layer of Germanium (Ge). This unique wafer technology enables placement of CS devices in arbitrary locations on the chip, while maintaining co-planarity with the CMOS for simple, high yield, monolithic integration. The first small-area InP HBTs fabricated on a germanium-on-insulator (GeOI) substrate are demonstrated. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.

Substrate Bowing : A Figure of Merit for AlGaN/GaN HEMTs Grown on Silicon? Yvon Cordier, Nicolas Baron, Sebastien Chenot, Olivier Tottereau, Mathieu Leroux, Fabrice Semond and Jean Massies (CRHEA-CNRS and Picogiga).

The aim of this work is to study, for varying growth conditions, how dislocations affect the residual strain and the resulting bowing of the Si(111) wafers. In a second step, we show how these two parameters correlate with the GaN buffer insulating properties as well as the 2-dimensional electron gas (2DEG) transport properties at the AlGaN/GaN interface of high electron mobility transistors (HEMTs). A first important result of this study is that a general trend exists with the final strain (the wafer bowing) evolving towards a more compressive state while reducing the threading dislocation density. At 300K, a mobility approaching 2000 cm2/V.s for a sample with a dislocation density of 5E9 cm-2 and a wafer bow of 14 µm (convex shape) is among the best results reported on Silicon.

International Solid State Circuits Conference (ISSCC, February 2008, San Francisco)

4.3 Migration of Cell Broadband EngineTM from 65nm SOI to 45nm SOI. O. Takahashi, C. Adams, E. Behnen, O. Chiang, S. Cottier, P. Coulman, J. Culp, G. Gervais, M. Gray, Y. Itaka, C. Johnson, F. Kono, L. Maurice, K. McCullen, L. Nguyen, Y. Nishino6, H. Noro, J. Pille, M. Riley, S. Tokito, T. Wagner, H. Yoshihara (IBM, Toshiba and Sony).

The paper describes the migration of the Cell Broadband EngineTM design from 65nm SOI to 45nm SOI.

Challenge/Significance: The migration of the 65nm SOI Cell Broadband EngineTM to 45nm SOI uses a mostly automated approach preserving cycle-by-cycle behavior. The design demonstrates the value to design efficiency and performance provided by improved process technologies. Power is reduced by 40% and area by 34%. The SRAM has a separate power supply to preserve cell stability, which overcomes one of the most troublesome aspects of process scaling. Extensive design for manufacturability techniques address increased variability in 45nm.

15.1: A CMOS-SOI 2.45GHz Remote-Powered Sensor Tag. S. Robinet, B. Gomez, N. Delorme (CEA-LETI/MINATEC).

A 0.13µm CMOS-SOI remote-powered pressure sensor tag for ambient intelligence or healthcare applications integrates a 2.45GHz RFID front-end and a ΔΣ sensor readout interface for use with a capacitive pressure transducer. It exhibits a 12 ENOB resolution, a 100Hz measurement bandwidth, and a reading distance of 40cm.

Challenge/Significance: Currently, monitoring of blood pressure, temperature and other variables used by healthcare professionals frequently require patients to be wired to recording equipment. Merging a 2.45GHz RFID tag with a pressure sensor allows wireless measurement of environmental variables. This extends the impact of RFID from product location and identification to wireless measurement and tracking of a large variety of important parameters like blood pressure, temperature, or heart rate.

21.2: A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management. H. Pilo, V. Ramadurai1, G. Braceras, J. Gabric, S. Lamphier, Y. Tan (IBM)

A 450ps access-time 512Kb SRAM macro is fabricated in 45nm SOI. Power improvements are achieved with little effect on performance and area. A two-stage, body-contacted sensing scheme along with other techniques achieve a 58% improvement in power consumption compared to the previous-generation macro. A single-device dynamic leakage-suppression scheme reduces leakage power by 37% with 1.8% area overhead and no wake-up cycle requirements.

Challenges this addresses: Multi-cycle dynamic power-management using NFET ground control requires large devices that increase area overhead. This also requires wake-up cycles before SRAM access. Large differential-data I/O bus causes considerable AC power consumption in high-performance SRAM macros. Domino sense-amplifier scheme in SOI using a single supply can no longer meet performance targets given large amounts of random SRAM-cell variation.

Significance: SOI SRAM macro enables state-of-the-art power specifications and performance at 45nm. This is a key SRAM building block for the 45nm high-performance ASIC library.

22.4: A Commercial Field-Programmable Dense eFUSE-Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. G. Uhlmann, A. Aipperspach, T. Kirihata, C. Kothandaraman, Y. Li, C. Paone1, B. Reed1, N. Robson, J. Safran, D. Schmitt1, S. Iyer (IBM)

A 99.999% sense-yield eFUSE supporting 0.6-to-1.2V read operation with in-hardware diagnostics for commercial VLSI design is implemented in a 64Kb one-time programmable-ROM test-chip. A 45nm SOI CMOS hardware reveals eFUSE programming ranges for VDD of 1.0 to 1.6V and VPRG of 1.2 to 1.8V with 99.999% yield.

Challenge/significance: A trend is the increasing use of one-time programmable electronic fuses to configure chips after manufacturing and to activate redundant blocks to repair defects. This trend is creating demand for efficient arrays containing large numbers of fuses with high reliability in the face of significant parameter variation. This paper from IBM details the design of a dense 64kb eFUSE array in 45nm SOI.

25.5: A 94GHz Locking-Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS. D. Kim, J. Kim, C. Cho (IBM).

A CML static divider operating up to 94.4GHz in 65nm SOI CMOS is presented. The operation range of the divider is extended by input-locking hysteresis and bias tuning. The locking hysteresis and sensitivity curve are analyzed, simulated, and measured. A 0.74dB hysteresis gain is observed. The divider consumes 15.8mW per flip-flop at 82.4GHz and the power-delay product per gate is 24fJ.

Challenge/significance: The papers in this session demonstrate high-speed performance and low power consumption realized in advanced process technologies. This paper from IBM uses a 65nm SOI CMOS process to implement a CML static divider working up to 94GHz, consuming only 15.8mW per flipflop at 82.4GHz.

IEEE International Electron Devices Meeting (IEDM, December 2007, Washington DC)

2.4: FBC’s Potential of 6F2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method Measuring Signal Sense Margin. F. Matsuoka, T. Ohsawa, T. Higashi, H. Furuhashi, K. Hatsuda, K. Fujita, R. Fukuda, N. Ikumi, Y. Minami, H. Nakajima, T. (Toshiba).

A 6F2 single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBC’s spacers can be optimized for making the SSM as large as 8muA at ± 4.5 sigma without sacrificing the retention time.

3.4: Strained FDSOI CMOS Technology Scalability Down to 2.5nm Film Thickness and 18nm Gate Length with a TiN/HfO2 Gate Stack. V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J.M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J.L. Autran and S. Deleonibus (CEA-LETI MINATEC and Soitec).

Scalability of both unstrained and strained FDSOI CMOSFETs is explored for the first time down to 2.5nm film thickness and 18nm gate length with HfO2/TiN gate stack. Off-state currents in the pA/mum range are achieved for 18nm short and 3.8nm thin MOSFETs thanks to outstanding electrostatic control: 67mV/dec subthreshold swing and 75mV/V DIBL. We demonstrate strain induced ION gain as high as 40% on the shortest transistors.

5.2: On the experimental determination of channel back-scattering in nanoMOSFETs. Zilli, M., Palestri, P., Esseni, D., Selmi, L. (U. Udine Italy).

By using accurate Multi-Subband-Monte-Carlo simulations of quasi-ballistic transport we carry out a detailed re-examination of the experimental extraction procedure for the ballistic-ratio BR=ID/IBAL in nanoMOSFETs. It is found that the ballistic-ratio extracted applying this procedure to the simulated drain current severely underestimates the BR extracted by directly comparing the simulated ID and IBAL.

6.6: Low Temperature Implementation of Dopant-Segregated Band-edge Metallic S/D Junctions in Thin-Body SOI p-MOSFETs. Larrieu, G., Dubois, E., Valentin, R., Breil, N., Danneville, F., Dambrine, G., Raskin, J.P., Pesant, J.C. (IEMN – UMR CNRS).

This paper proposes the implementation of a dopant segregated band-edge silicide using implantation-to-silicide and low temperature activation (500 °C). The integration of platinum silicide coupled to boron segregation demonstrates a 50% enhancement of the current drive over the dopant-free approach. RF characterization unveils a cut-off frequency fT of 180GHz at Lg=30nm without application of channel stressors.

7.6: Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance. S. Kolluri, K. Endo, E. Suzuki and K. Banerjee (UC Santa Barbara and AIST).

A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions. The model has been applied to carry out a detailed sensitivity analysis of self-heating with respect to various FinFET parameters and structures which are critical for improving circuit performance and EOS/ESD reliability.

8.4: Impact Ionization Nanowire Transistor with Multiple-Gates, Silicon-Germanium Impact Ionization Region, and Sub-5 mV/decade Subtheshold Swing. E.-H. Toh, G.H. Wang, M. Zhu, C. Shen, L. Chan, G.-Q. Lo, C.-H. Tung, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C. Yeo (National University of Singapore, Institute of Microelectronics and U. Michigan).

The paper reports the first demonstration of an Impact Ionization nanowire multiple-gate field-effect transistor (I-MuGFET or I-FinFET). Excellent subthreshold swing of sub-5 mV/decade at room temperature was achieved. The multiple- gate structure enhances the impact ionization rate in the fin or nanowire channel, reduces the breakdown voltage and improves device performance.

10.4: Record RF Performance of 45-nm SOI CMOS Technology. Sungjae Lee Jagannathan, B., Narasimha, S., Chou, A., Zamdmer, N., Johnson, J., Williams, R., Wagner, L., Jonghae Kim, Plouchart, J.-O., Pekarik, J., Springer, S., Freeman, G. (IBM).

This paper reports record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT’s of 485GHz and 345GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fT’s are the highest ever reported in a CMOS technology. Body-contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245GHz with no degradation in critical analog figures of merit, such as self-gain.

10.7: Fully-Depleted SOI Technology using High-K and Single-Metal Gate for 32nm Node LSTP Applications featuring 0.179µm2 6T-SRAM bitcell. C. Fenouillet-Beranger, S.Denorme, B. Icard, F. Boeuf, J. Coignus, O. Faynot, L. Brevard, C. Buj, C. Soonekindt, J. Todeschini, J.C. Le-Denmat, N. Loubet, C. Gallon, P. Perreau, S. Manakli, B. Minghetti, L. Pain, V.Arnal, A. Vandooren, D. Aime, L.Tosti, C. Savardi, M. Broekaart, P. Gouraud, F.Leverd, V. Dejonghe, P. Brun, M. Guillermet, M. Aminpur, S. Barnola, F. Rouppert, F. Martin, T. Salvetat, S. Lhostis, C. Laviron, N. Auriac, T. Kormann, G. GChabanne, S. Gaillard, O. Belmont, E. Laffosse, D. Barge, A. Zauner, A. Tarnowka, K. Romanjec,H. Brut, A. Lagha, S. Bonnetier, F. Joly, N. Mayet, A. Cathignol, D. Galpin, D. Pop, R. Delsol, R. Pantel, F. Pionnier, G. Thomas, D.Bensahel, S. Deleonibus, T. Skotnicki, H. Mingam (STMicroelectronics, NXP, Freescale, CEA-LETI MINATEC).

This paper reports on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good Ion/Ioff performance for nMOS and pMOS transistors in the ultra-low-leakage regime (Ioff=6.6 pA/mum) are presented. In addition co-integration of high voltage devices with EOT 29A/Vdd 1.8 V are made. For the first time, the functionality of 0.248mum and 0.179mum2 6T-SRAM bit-cells is demonstrated on FDSOI technology with a high-k/metal gate stack.

11.8 (Late papers): 45nm SOI CMOS Technology with 3X Hole Mobility Enhancement and Asymmetric Transistor for High Performance CPU Application. S.K.H. Fung, H.C. Lo, C.F. Cheng, W.Y. Lu, K.C. Wu, K H. Chen, D. H. Lee, Y.H. Liu, I.L. Wu, C.T. Li, C.H. Wu, F.L. Hisao, T. L. Chen, W.Y. Lien, C.H. Huang, P.W. Wang, Y.H. Chiu, L.T. Lin, K.Y. Chen, H.J. Tao, H.C.Tuan, Y.J. Mii, Y.C. Sun (TSMC).

45nm SOI CMOS technology target for high performance CPU application is reported. Process induced strained CMOS demonstrates 1232/855uA/um DC Ion at 100nA/um Ioff under Vdd=1V, which is the highest ever reported performance at 45nm ground rule for both SOI and bulk technology. Small width PFET reaches record high 975uA/um. High SiGe over Si volume ratio in thin film SOI enables high compressive stress even at small device width and active area. Hole mobility is enhanced by 3X and Ion is increased 2X. On top of record high drive current, asymmetric transistor is implemented to further improve energy-delay by 20%. Our 45nm SOI technology offers industry leading performance in terms of speed, energy and density.

15.6: Characterisation of AlGaN/GaN HEMT Epitaxy and Devices on Composite Substrates. G. Meneghesso, C. Ongaro, E. Zanoni, C. Brylinski, M. A. Poisson, V. Hoel, J.C. de Jaeger, P. Bove, J. Thorpe (Universita di Padova, Alcatel-Thales, IEMN/TIGER, Picogiga, UMS).

This paper shows results obtained on AlGaN/GaN FJEMTs processed on epitaxy grown on composite substrates. The results are very promising for the fabrication of low cost high power microwave transistors for wireless communication systems. The composite substrates constitute a valuable alternative to the silicon since better thermal properties are expected.

18.3: Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture. R. Tsuchiya, T. Ishigaki, Y. Morita, Y. Yamaoka, T. Iwamatsu, T. Ipposhi, H. Oda, N. Sugii, S. Kimura, K. Ito, Y.Inoue (Renesas and Hitachi).

45nm-gate SOTB (silicon on thin BOX) technology for LSTP application has been successfully developed. In the SOTB device, short-channel effect immunity without channel doping and back-gate bias threshold voltage (Vth) control are demonstrated. We have also proposed the SOTB device design enabling the controllable inverter delay and low Vth fluctuation for logic and SRAM memory cell transistors. Inverter delay can be improved from 19.3 to 10.5 ps by applying the forward back-gate bias. Furthermore, Vth fluctuation can be reduced about 16% by applying the reverse back-gate bias. A 6-transistor SRAM memory cell of the SOTB structure by adding a reverse back bias control has shown to dramatically improve SRAM memory cell stability.

18.4: Measurements of Inter-and-Intra Device Transient Thermal Transport on SOI FETs. P.M. Solomon, M. Shamsa, K.A. Jenkins, C. P. D’Emic, A.A. Balandin and W. Haensch (IBM and English University).

This paper reports on the first resolving detailed thermal transients for CMOS devices. Furthermore we investigate different heat paths between and inside devices to reveal the importance of the thermal conductivity of the gate. We show both by measurements and simulations that oxide does not afford good isolation and that the main cooling mechanism of SOI devices is to the gate, with transfer resistance playing an important role.

18.5: An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits. Klaus von Arnim, Christian Pacha, Karl Hofmann, Thomas Schulz, Klaus Schrüfer, and Jörg Berthold (Infineon).

A new methodology to assess dynamic circuit performance using basic device currents is presented. The relevance of currents in the linear regime for circuit performance in sub-65nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.

21.5: A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation, Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad and Chenming Hu (UC Berkeley).

A compact model for multi-gate MOSFETs with two independently-biased gates is presented. The use of the model is demonstrated through two simulation examples: (1) Back-gate dynamic feedback of FinFET SRAM cells and (2) Tuning of device variations through back gate biasing.

24: Leakage Reduction in Sub-100nm CMOS Technologies: Bridging the Gap Between Technology, Circuit Design and Low Power Product Requirements. Christian Pacha, Joerg Berthold (Infineon).

With the introduction of the 130nm and 90nm CMOS technology nodes leakage reduction techniques became an essential topic of circuit and system design to meet product requirements, especially in the fields of portable applications. At the same time, a diversification into CMOS technology platforms for low standby power applications, so-called generic CMOS platforms, and high performance CMOS technologies for high-speed microprocessors is observed.

27.2: Gatestacks for Scalable High-Performance FinFETs. G. Vellianitis, M.J.H. van Dal, L. Witters, G. Curatola, G. Doornbos, N.Collaert, C. Jonville, C. Torregiani, L. S. Lai, J. Petry, B.J. Pawlak, R. Duffy, M. Demand, S. Beckx, S. Mertens, A. Delabie, T. Vandeweyer, C. Delvaux, F. Leys, A. Hikavy, Rooyackers, R., Kaiser, M., Weemaes, R.G., Voogt, F., Roberts, H., Donnet, D., Biesemans, S., Jurczak, M., Lander, R.J.R. (NXP-TSMC Research Centre).

Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch.

27.3: Route to Low Parasitic Resistance in MuGFETs with Silicon-Carbon Source/Drain: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing. R.T-P Lee, A.T-Y Koh, F-Y Liu, W-W Fang, T-Y. Liow. K-M. Tan, P-C. Lim, A.E-J. Lim, M-Z. Wong H. Shing, K-M. Hoe, C-H. Tung, G-Q. Lo, X. Wang, D.K-Y. Low, G.S. Samudra, D-Z. Chi and Y-C. Yeo (National University of Singapore and Institute of Mat).

This paper reports the demonstration of two distinct approaches to reduce parasitic resistances in MuGFETs with silicon-carbon (Si:C) S/D. First, the addition of dysprosium (Dy) in NiSi:C contacts reduces the electron barrier height by 38% on SiC. Device integration of the Ni(Dy)Si:C contacts provides a 30% reduction in series resistance leading to improved IDsat performance. Second, we also report the first demonstration of pulsed laser annealing (PLA) for MuGFETs with Si:C S/D for enhanced dopant activation, leading to ~50% lower series resistance.

28.1: Extension of Universal Mobility Curve to Multi-Gate MOSFETs. Yoshimoto, H., Sugii, N., Hisamoto, D., Saito, S.-i., Tsuchiya, R. Kimura, S. (Hitachi).

The concept of “universal mobility” was successfully extended to multi-gate transistors. We developed a novel method to determine the effective electric field (Eeff) in multi-gate transistors experimentally taking all charges in and around the silicon body into account. By applying this method to double-gate (DG) transistors, we showed that Eeff goes from positive to negative, which depends on whether the front- or back- side channel is dominant. The validity of the universal relationship between mueff and Eeff was confirmed even with negative Eeff. Moreover, in the case of a symmetric DG transistor (Vfg=Vbg) like FinFETs, a high mueff can be obtained even at high gate-overdrive voltages because Eeff is always approximately zero.

28.2: More-than-Universal Mobility in Double-Gate SOI p-FETs with Sub-10-nm Body Thickness -Role of Light-Hole Band and Compatibility with Uniaxial Stress Engineering. Shigeki Kobayashi, Masumi Saitoh, Ken Uchida (Toshiba).

We investigated hole mobility enhancement by double gate (DG) mode in (001)/<110> ultrathin-body SOI p-FETs with sub-10nm SOI thickness (TSOI). It was found hole mobility in DG mode is greatly enhanced in all the measured TSOI in comparison with single gate mode. Mobility in DG mode of sub-10nm TSOI exceeds even the universal mobility at high surface carrier densities. The higher mobility in DG mode is attributed to the average effective mass reduction due to the population increase in light hole band. Subband calculations confirmed this model. It was also demonstrated higher mobility in DG mode is further enhanced by uniaxial stress.

28.4: Mobility Enhancement in Uniaxially Strained (110) Oriented Ultra-Thin Body Single- and Double-Gate MOSFETs with SOI Thickness of less than 4 nm. K. Shimizu and T. Hiramoto (University of Tokyo).

Mobility in single-gate (SG) and double-gate (DG) ultra-thin body (UTB) SOI MOSFETs under uniaxial tensile stress has been systematically examined. Mobility enhancement in both UTB nMOSFETs and pMOSFETs by stress is experimentally demonstrated for the first time. The enhancement in UTB nMOSFETs is larger than the prediction by theory. The mobility enhancement by stress in DG UTB nMOSFETs and pMOSFETs is also observed. The enhancement may originate from not only the subband energy shift but effective mass change.

30.7: Single-Electron Circuit for Stochastic Data Processing Using Nano-MOSFETs. K. Nishiguchi, A. Fujiwara (NTT),

A MOSFET-based circuit utilizing single electrons is demonstrated at room temperature. Individual electrons randomly passing through the nanoscale silicon-on-insulator (SOI) MOSFET are monitored by an electrometer in real time. The present result promises new single-electron applications using nanoscale MOSFETs.

32.1: Three Technologies for a Smart Miniaturized Gas-Sensor: SOI CMOS, Micromachining and CNTs – Challenges and Performance. F. Udrea, J.W. Gardner, J. Park, M.S. Haque, S.Z. Ali, P.K. Guha, S.M.C. Vieira, H.Y. Kim, S.Y. Lee, S. H. Kim, Y. Choi, K.C. Kim, S.E. Moon, W.I. Milne, and S. Maeng (University of Cambridge, University of Warwick, Electronics and Telecommunications Research Institute).

In this paper we propose a new type of solid-state gas sensor by combining three recent advances, namely silicon-on-insulator CMOS technology, through wafer etching and growth of gas-sensitive carbon nanotubes. We have developed novel tungsten-based CMOS micro-hotplates that offer ultra low power consumption (less than 10mW at 250 °C), on-chip CNT deposition at temperatures up to 700 °C, and full integration of CMOS circuitry. We believe that our approach is attractive for the mass production of low-cost, low-power gas sensors in silicon foundries.

34.1: Observation of Mobility Enhancement In Strained Si And Sige Tri-Gate MOSFETs with Multi-Nanowire Channels Trimmed by Hydrogen Thermal Etching. T. Tezuka, E. Toyoda, S. Nakaharai, T.Irisawa, N. Hirashita, Y. Moriyama, N. Sugiyama, N. Taoka, Y. Yamashita, O. Kiso, M. Harada, T. Yamamoto and S. Takagi (MIRA-ASET, Covalent Materials, MIRAI-AIST)

Strained Si and SiGe tri-gate nanowire (NW) MOSFETs with significantly reduced line-edge roughness and smooth sidewalls were fabricated by a novel anisotropic thermal etching technique in H2 atmosphere. Effective carrier mobility measurements revealed mobility enhancements for the strained-Si NW n-MOSFETs and the strained-SiGe NW p-MOSFETs by factors of 1.9 and 1.6 against unstrained Si NW n- and p-MOSFETs, respectively. It was also shown that the sidewall shapes of the NWs have a great impact on the mobility via the difference in the surface roughness scattering on the sidewalls.

34.6: Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and Beyond. J. Cai, A. Majumdar, D. Dobuzinsky, T.H. Ning, S. Koester, and W. Haensch (IBM).

This paper reports on 65nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current IOFF down to 10pA/um at supply voltage VDD = 1.2V. NFET/PFET drive current IDSAT = 550/250µA/µm at IOFF = 100pA/µm and gate length LG ~ 55 nm are achieved with a single tensile liner film. Our result suggests that there are no fundamental limits for low leakage application of SOI.

35.4: New Generation of Z-RAM. S. Okhonin, M. Nagoga, E. Carman, R. Beffa, E. Faraoni (Innovative Silicon and PSE-B Lausanne).

A new generation of the single transistor floating body DRAM is introduced for the first time. The new memory is largely based on the bipolar transistor existing in the MOS structure. The memory’s main features are high margin, low-power consumption, and scalability.

35.5: A Unified-RAM (URAM) Cell for Multi-Functioning Capacitorless DRAM and NVM. Jin-Woo Han, Seong-Wan Ryu, Chungjin Kim, Sungho Kim, Maesoon Im, Sung Jin Choi, Jin Soo Kim, Kwang Hee Kim, Gi Sung Lee, Jae Sub Oh, Myeong Ho Song, Yun Chang Park, Jeoung Woo Kim, and Yang-Kyu Choi (Korea Advanced Institute of Science & Technology).

A novel partially-depleted (PD) SONOS FinFET is demonstrated for unified function of a high speed capacitorless IT-DRAM and non-volatile memory (NVM). A floating body and O/N/O layer are combined in a single FinFET to provide multi-functional unified-RAM (URAM) operation. The fabricated URAM shows a VT window of 3V with a retention time exceeding 10 years for NVM operation and a sensing margin of 9muA with a program/erase time of 10nsec for IT-DRAM operation in a single memory cell transistor.

36.2: Physical Model for NAND Operation in SOI and Body-Tied Nanocrystal FinFLASH Memories. L. Perniola, E. Nowak, G. Iannaccone, P. Scheiblin, C. Jahan, G. Pananakakis, J. Razafindramora, B. De Salvo, S. Deleonibus, G. Reimbold, F. Boulanger (CEA-LETI, Universita di Pisa and IMEP/INPG Grenoble).

A semi-analytical model for nanocrystal-based FinFLASH memories under uniform stress is presented. This model investigates the essential features related to the non-uniform trapped charge distribution in both body tied and SOI devices. Main conclusions concern the different characteristic times of charge trapping over fin corners or planar fin regions.

38.2: Development of a Production-Ready, Back-Illuminated CMOS Image Sensor with Small Pixels. T, Joy, S. Pyo, S. Park, C. Choi, C. Palsule, H. Han, C. Feng, S. Lee, J. McKee, P. Altice, C. Hong, C. Boemler, J. Hynecek, J. Lee, D. Kim, H. Haddad, and B. Pain (Magnachip).

Manufacturing feasibility of a back-illuminated (BSI) CMOS image sensor has been demonstrated using a special SOI starting wafer. Unlike a traditional BSI process, wafer-level thinning – requiring no post-thinning passivation step – is accomplished. Measured data from a 2 megapixel BSI sensor exhibits comparable dark current but almost 3 times higher quantum efficiency (QE) and sensitivity than a conventional sensor.

Late News: Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node, Kazuya Ohuchi, Christian Lavoie, Conal Murray, Chris D’Emic, Isaac Lauer, Jack O. Chu, Bin Yang, Paul Besser, Lynne Gignac, John Bruley, Gilbert U. Singco, François Pagette, Anna W. Topol, Michael J. Rooks, James J. Bucchignano,Vijay Narayanan, Mukesh Khare, Mariko Takayanagi, Kazunari Ishimaru , Dae-Gyu Park, Ghavam Shahidi and Paul Solomon. (Toshiba and IBM).

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10-8 Omega-cm2 for both n+ and p+ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.

EuroSOI 08 / Fourth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (Tyndall National Institute, Cork, Ireland, January 2008)

Z-RAM memory technology. S. Okhonin, M. Nagoga (Innovative Silicon, PSE-B Lausanne).

The current status of the single transistor DRAM (Z-RAM) technology is reviewed and the new generation of Z-RAM is described.

Estimations of the Ion-Ioff Performances of Nano nMOSFETs with Alternative Channels Materials. Quentin Rafhay, Raphaël Clerc, George Pananakakis and Gérard Ghibaudo (IMEP-LAHC, INPG-UJF-CNRS, Minatec).

In this work, the impact of light conduction band effective masses on Ion-Ioff performances of Nano nMOSFET has been re-investigated by the mean of simple analytical models. Contrary to previous studies, because of the enhancement of Source to Drain Tunneling (SDT) and the degradation of quantum capacitance in light effective masses materials (like GaAs and Ge), Si based devices turn out to offer an acceptable Ion-Ioff trade off for the last node of the roadmap.

In-depth characterization of quantum effects in SOI MOSFETs for modeling purposes. J. B. Roldán, M. Balaguer, A. Godoy, F. G. Ruiz, F. Gámiz (Universidad de Granada).

A detailed quantitative study of the inversion charge obtained by means of classical and quantum simulation tools has been performed in order to analyze the need of the inclusion of quantum mechanical effects (QME) in compact models of different SOI transistors. The differences obtained between the classical and quantum charge distributions are higher in (Surrounding Gate Transistors) SGTs than in DGMOSFETs (Double Gate MOSFETs) due to the higher confinement of the inversion charge in SGTs.

Review of Advanced Substrate Trends. L. Clavelier, C. Deguet, F. Andrieu, C. Le Royer, Y. Letiec, M. Kostrzewa, J.P. Mazellier, A. Tauzin, J.S. Moulet, F. Fournel, O. Faynot, F. Letertre, I. Cayrefourq, B. Ghyselen, C. Mazuré. (CEA-LETI MINATEC and Soitec).

A brief review of advanced substrates developed using the Smart CutTM technology. Today R&D on advanced substrates is focused on the integration of new materials and functionalities in order to improve devices performances and enlarge application spectrum. This paper deals with advanced substrates for: “More MOORE” (active layer engineering and Buried Oxide (BOx) Engineering); “More Than MOORE” (such as Lithium Tantalate On Metal On Insulator substrate (LTMOI) for RF MEMS), and future “beyond CMOS” substrates (such as a selective strain etching solution on “twisted substrates”).

Temperature Behavior of Spiral Inductors on High Resistivity Substrate in SOI CMOS Technology. M. El Kaamouchi, M. Si Moussa, J.-P. Raskin, and D. Vanhoenacker-Janvier (Université catholique de Louvain).

This paper reviews and analyzes a physical model for integrated planar spiral inductors on high resistivity substrate in Silicon-on-Insulator. SOI CMOS technology has become a competitive technology for radio transceiver implementation of various wireless communication systems due mainly to low-power, low-cost, higher level of integratability, high performance mixed-mode circuits, etc. Now, an increase number of integrated inductors are required for building compact analog blocks of multi-standard mixedmode IC’s. In this paper, a model is built to characterize the behavior of planar spiral inductors on High Resistivity (HR) SOI at high temperature.

Gate Oxide Integrity on SOI. Paul Daly, Shay Whiston (Analog Devices).

This paper addresses one of the challenges involved in combining high performance bipolars with low geometry CMOS on a single process. Dielectric isolation of bipolars to substrate is essential for optimising their high frequency performance, and is achieved by using SOI wafers. ADI’s new process platform will offer foundry compatible 0.35um CMOS with ADI’s high voltage CMOS (16V and 30V) and high performance double poly bipolars at various voltage ratings. Unlike previous generation processes, bipolar isolation to substrate is provided by use of trench and bonded wafers. This migration to SOI for improved bipolar performance has consequences for the processing of CMOS on the flow. One of the risks inherent in the development of the next generation process platform at ADI was identified at the outset of the process development: gate oxide quality on SOI material due to reduced gettering. The various options available for overcoming this challenge have or are being investigated. This work will ensure that reliable gate oxides can be achieved on all process options of ADI’s new process platform as they are released for production during the coming year.

3-D capacitive MEMS sensors co-integrated with SOI CMOS circuits. N. André a, B. Ruea, C. Renauxa, D. Flandrea and J.-P. Raskina (Université catholique de Louvain).

A SOI CMOS compatible process, guaranteed by use of classical CMOS materials and fabrication techniques and demonstrated with fabrication of a complete functional circuit, is presented. From our Fully Depleted (FD) SOI CMOS process, addition of only one mask (3 lithographic steps) is needed to obtain a flow sense MEMS-based circuit.

On the switching speed of SOI LEDs. Jurriaan Schmitz, Roel de Vries, Cora Salm, Tu Hoang, Ray Hueting, and Jisk Holleman (University of Twente).

Recently, we presented a novel design for a silicon LED in SmartCUTTM SOI wafers. It exhibits a record quantum efficiency for SOI-based silicon LEDs and opens the way to the integration of light emitters in a VLSI process on SOI. In this paper, we present first experimental and modeling results showing that this new design has the potential to switch on and off faster than 1MHz – sufficiently fast for several commercial applications such as an integrated optocoupler.

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