TSMC Reports Industry-Leading Performance
Posted date : May 14, 2008

The world’s biggest foundry says its 45nm SOI process technology for the newest generation of high performance CPUs is the best in terms of speed, energy and density in chips using standard nitrided oxide for the gate dielectric.

In terms of speed, energy and density, at TSMC we believe we have developed the industry’s best 45nm SOI process technology among all reported MOSFETs with nitrided oxide. The supporting data was presented by our R&D group at IEDM 2007, in a paper entitled 45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application (Samuel K.H. Fung, et al).

Our results differ from the high-k and metal gate solutions reported elsewhere in the industry but, at the same time, do not add significant cost and complexity that these new materials entail.

This 45nm SOI CMOS technology targets high performance CPU applications. As indicated in the paper:

  • This process-induced strained CMOS demonstrates the highest performance at the 45nm ground rule for both SOI and bulk technology among all reported MOSFETs with nitrided oxide.
  • Our small-width PFET has reached a record high compressive stress.
  • We have tripled hole mobility and doubled Ion.
  • On top of the record high drive current, an asymmetric transistor has been implemented to further improve energydelay by 20%.

Embedded SiGe and standard gate dielectric

Process keys to enhancing the device include:

  • embedded SiGe (e-SiGe),
  • stress memorization effect (SMT),
  • dual-embedded stress liner (DESL) and
  • millisecond laser (ms) annealing.

The device uses a standard gate dielectric of nitrided oxide.

Highest performance NFET and PFET

Both the NFET and PFET in this work demonstrate the highest Ion-Lg performance ever reported at 45nm with nitrided oxide. The PFET performance is 14% higher than the highest previously reported.

TEM: transistor cross-section, TSMC’s 45nm SOI CMOS technology.

In scaling from 65nm to 45nm, gains in circuit performance are due mainly to the PFET. NFET improvement is the result of scaled spacer and fine tuning of SMT/ms anneal.

With our record-breaking high current drive (see Table 1) at very short Lg together with aggressive contacted poly pitch, we believe that our performance outperforms other published 45nm SOI technology in terms of intrinsic transistor speed, energy and gate density.

Our champion e-SiGe process improves PFET Ion by 41% on top of DESL. The fact that 3X hole mobility is achieved in our Si at 45nm DR poly pitch and active area is really stunning.

In moving from a wide to a narrow device, the PFET attains a higher Ion in SOI technology due to the beneficial DESL boundary effect in the Y-direction. Thin film SOI together with aggressive SiGe proximity allows very high SiGe-to-Si volume ratio in a dense poly pitch and small active area. Using e-SiGe for I/O PFET can lower I/O driver power by roughly 20%.

Scaling: SOI performance boost retained

This work demonstrates that SOI transistor DC performance continues to advance in the same way as bulk. We can conclude that SOI’s relative performance boost of 10-20% (compared to best-of-class bulk device performance) is retained with scaling.

Table 1. This work delivers industry leading CMOS performance in terms of speed, energy and density.

* AFET intrinsic delay and energy-delay is calibrated using silicon ring data. [2] S. Narasimha et al., IEDM 2006.

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