3D at the Wafer Level
Posted date : Jul 16, 2008

Soitec’s core technologies are building blocks for 3D integration.

At the wafer level, molecular bonding techniques and Smart Cut technology add significant value to 3D integration. A good application for these building blocks is backside illuminated image sensors (BIS), which is probably the most mature 3D technology and close to mass production.

For standard front side illuminated imagers the photodiode quantum efficiency (QE) suffers with decreasing pixel size and an increasing number of metal layers. The industry has identified BIS as the path to keep increasing pixel density, resolution and speed without sacrificing QE.

After imager fabrication, the processed wafer is bonded to a handle wafer and the original substrate is thinned down leaving only few microns of silicon and exposing the photodiodes. In this way the exposure to light of the photodiodes can be maximized, translating into a very high QE.

Molecular bonding and IC layer transfer are enabling techniques that make possible the fabrication of BIS without die deformation and post-processing by the imager maker. We have developed low-temperature bonding techniques that are compatible with the aggressive wafer grinding and thinning processes and meet the requirements for IC post processing.

BIS imagers take full advantage of this core know-how. Moreover, if SOI wafers are initially used to fabricate the imagers then the overall process becomes less complex and more robust. The buried oxide of the SOI wafer acts as a built-in etch stop during the substrate removal process and protects the active Si layer of the photodiodes.

Bonding expertise

Stacking layers of CMOS devices pre-interconnect formation is another very interesting application for Smart Cut technology and low temperature molecular bonding. The challenges here are even bigger because the transferred layer will go through a full CMOS fabrication step.

The pre-existing CMOS device layer limits bonding temperatures to below 850°C. If the underlying layers happen to already have interconnects the situation is even tougher because bonding temperatures cannot go beyond 450°C.

The knowledge and experience in the development of engineered substrates, with buried metal structures and strong CTE mismatch, brings valuable synergy to this 3D technology, an enabling Soitec know-how.
Finally, fully processed wafer-to-wafer bonding including wafer-to-wafer alignment is a building block in development that will enable more complex 3D architectures.

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