Defect-Free High-Temperature Processing
Posted date : Jul 16, 2008

Innovations in RTP play a key role in SOI wafer production for 45nm and beyond.

Rapid Thermal Processing (RTP) was introduced in silicon-on-insulator (SOI) wafer production for surface smoothing to combine thickness control and surface quality assurance.

For sub-45nm technology node defect-free processing, RTP is an important step in the production cycle, as specifications become critical with respect to crystal defect reduction, particularly on the backside of the wafer. Stringent lithography requirements and yield concerns require total defect- and stress-free processing.

Technology innovation

The temperature non-uniformity limit over the 300-mm substrate, independent of bulk or SOI, approaches 3 to 5°C, while the maximum annealing temperature approaches the melting point of silicon for improved surface smoothing performances. These groundbreaking changes to meet future technology requirements drive important innovations and at the same time, present unique challenges for equipment manufacturers.

One of the new technologies introduced to RTP systems is a rotating susceptor (wafer support) technology.

Figure 1. View into Mattson’s Helios™ RTP chamber with rotating susceptor for high temperature processing up to 1280°C in controlled ambient.

Figure 1 shows a Helios 300mm RTP chamber with a supporting susceptor for crystal defect-free high temperature processing. The “wafer on top of susceptor” layout ensures defect-free processing at temperatures as high as 1280°C for several seconds. No backside marks or slip lines at the wafer edge are detectable on SOI or bare silicon wafers as characterized with Surfscan SP1 technology or Nanotopology analysis after processing at 1230°C or higher for several seconds

This unique processing feature is important for the wafer manufacturing industry. The entire RTP system must not only precisely control the process for SOI or bare silicon substrates, it must also be reliable and repeatable at an acceptable cost per wafer for a variety of customers in the silicon substrate manufacturing arena, allowing the industry to keep on track with the ITRS roadmap.

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