At Semicon West 08
Posted date : Dec 3, 2008

At Semicon West 08, Soitec announced a new advanced SOI substrates for the sub-45nm roadmap (partially depleted, fully-depleted and multi-gate (FinFET, Trigate) devices). The top silicon layer can range from just 20nm up to 110nm, while the BOX can be as thin as 10nm. High Resistivity options are generation of also available.

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