Transferring the entire layer of circuits from a processed wafer to the best substrate for the application is now available for custom manufacturing or technology transfer.
The Soitec Group recently announced that Smart Stacking™, our circuit stacking technology, is ready for both manufacturing and technology transfer.
This low-temperature industrial process from Soitec’s Tracit business unit achieves wafer-level circuit stacking onto a range of starting materials with excellent yield. The ability to move a finished circuit onto another carrier without jeopardizing yield opens new doors for designers.
Smart Stacking enables the stacking of several layers in order to obtain 3D structures or to enhance circuit performance by using a “handle substrate” adapted to the application. For example, options pertaining to transparency, resistivity and thermal conductivity are of interest for fields like displays, RF and power applications.
Image sensor designers are among the first to recognize the value of Smart Stacking™, leveraging it for backside illumination (BSI) technology. It is also being tapped for a range of new photonics applications, RF circuits and microwave components, CMOS logic and memories, power ICs and solid-state lighting.
Upcoming generations of complex 3D product architectures integrating heterogeneous components are also enabled by Smart Stacking technology.
The Smart Stacking™ platform was developed through a practical combination of pioneering materials research and high-volume production know-how. As such, it enables high throughput manufacturing solutions for wafer-to-wafer stacking, with the ability to transfer very thin layers.
Stacking processed or semi-processed wafers drastically reduces the thermal process window for bonding. Therefore, Smart Stacking uses low temperature, low stress and high-energy wafer bonding. This secures both high yield and high reliability.
Smart Stacking is scalable to all available wafer sizes, and is adaptable to a range of starting materials, including various silicon options, SiO2, Si3N4, fused silica, glass, and polycrystalline silicon carbide.
The use of molecular bonding technology avoids any glue or thermo-compression. In addition to enabling high throughput, it minimizes stress on the devices.
It also helps prevent wafer deformation that might cause misalignment or distortion issues. This is particularly important for subsequent processing using photolithography.
A second key feature is the thickness control in transferring very thin (from 10µm down to sub-micron) and uniform layers. This enables very dense TSV connections.
To serve the full range of customer requirements, Soitec is providing both manufacturing service and technology licensing options.
For lower volume applications, we offer circuit stacking manufacturing services in our state-of-the-art manufacturing line. Several wafer types coming from a number of worldwide foundries and IDMs have already been successfully processed for prototyping and production.
However, higher volume applications may be served best by transferring a customized process to our customers, giving them opportunities to simplify their logistics, reduce costs and shorten cycle times. In these cases, technology licensing is an attractive option.
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