IEDM
Posted date : May 27, 2009

http://www.his.com/~iedm/

San Francisco, December 2008

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here is a comprehensive listing of the papers of interest to the SOI and advanced substrates community.

• Comprehensive Study on V_th Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation. N. Sugii, et al.  (Hitachi)
  Silicon on Thin BOX (SOTB) for high-speed, low-power SOCs has the smallest V_th variation among all planar CMOS structures.  Researchers have now found ways to reduce threshold voltage variation even further.  (Read the full story in ASN#12 )
• High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding. O. Weber, et al. (Leti/ST/Soitec)
  Undoped FD-SOI architectures are extremely effective in controlling V_t variability.  Variation in the thickness of the top silicon is found not to be a significant factor in V_t variation; rather, thinning the top silicon minimizes V_t fluctuations.  (Read the full story in ASN#12)
• 22 nm Technology Compatible Fully Functional 0.1 µm2 6T-SRAM Cell. B. S. Haran, et al. (IBM/Freescale/AMD)
  Researchers from the IBM Alliance describe the world’s smallest fully functional SRAM memory cell. This work suggests that SRAM technology can be extended on planar SOI.
• Autonomous Refresh of Floating Body Cell (FBC). T. Ohsawa, et al. (Toshiba)
  The physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without a sense amplifier operation. Therefore, FBC can be used to realize static RAM without periodical refresh while retaining data.
• First Observation Of Finfet Specific Mismatch Behavior And Optimization Guidelines For SRAM Scaling. T. Merelle, et al. (NXP/TSMC/IMEC)
  Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. This study provides guidelines for SRAM design in a FinFET technology.
• 190V N-Channel Lateral IGBT Integration in SOI 0.35µm BCD Technology. M. Sambi, et al. (STMicroelectronics)
  The integration of 190V N-Ch. LIGBT in SOI 0.35μm shrunk BCD technology is described. The novel device shows a very high saturation current and good HTRB robustness.
• Implementation and Optimization of Asymmetric Transistors in Advanced SOI CMOS Technologies for High Performance Microprocessors. J. Hoentschel, et al. (AMD/U.Dresden)
  Sub-40nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65nm and 45nm PD-SOI CMOS technologies. Product-level implementation shows a speed benefit of 12%.
• Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature. J. Chen, et al. (U.Tokyo)
  Accurate electron mobility in nanowires on (110) SOI has been achieved by the split C-V method for the first time.
• Silicon Photonic Modulator and Integration for High-speed Applications. (Invited)  L. Liao, et al. (Intel/Numonyx)
  Researchers presented recent results of a silicon photonic integrated chip that is capable of transmitting data at an aggregate rate of 200 Gb/s. This is a continuation of the SOI-based work that Ansheng Liu of Intel wrote about in ASN8.
• Impact of SOI, Si1-xGexOI and GeOI Substrates on CMOS Compatible Tunnel FET Performance. F. Mayer, et al (CEA-LETI)
  This paper reports on the first experimental investigations in SOI, Si1-xGexOI & GeOI Tunnel FET (TFET).  The devices were fabricated using a FD SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS.
• Improved Effective Switching Current (IEFF+) and Capacitance Methodology for CMOS Circuit Performance Prediction and Model-to-Hardware Correlation. X. Yu, et al. (IBM)
  This paper demonstrates new effective drive current IEFF + methodologies to address predictability of circuit performance across wide V_t range and accuracy of effective resistance REFF prediction-to-hardware correlation.
• Setting up 3D Sequential Integration for Back-Illuminated CMOS Image Sensors with Highly Miniaturized Pixels with Low Temperature Fully Depleted SOI Transistors. P. Coudrain, et al. (STMicroelectronics, CEA LETI-MINATEC, Institut Superiéur de l’Aéronautique et de l’Espace)
  This paper presents an innovative 3D BSI architecture capable of overcoming pixel miniaturization drawbacks.
• On The Difference of Temperature Dependence of Metal Gate and Poly Gate SOI MOSFET Threshold Voltages. S.-J. Han, et al. (IBM)
  The temperature dependence of device performance is a critical factor that determines overall product power-performance. The paper shows HKMG gate stacks drive significantly higher threshold temperature dependence over poly-Si/SiON. In SOI, the work-function engineering enabled by HKMG integration schemes can result in even higher Vt temperature sensitivity attributed to differences in floating body behavior. The combined effects result in higher drive current at elevated temperature.
• Gate Length Scaling and High Drive Currents Enabled for High Performance SOI Technology using High-k/Metal Gate. K. Henson, et al. (IBM, Freescale, AMD)
  CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25nm, highlighting the scalability of this approach for high performance SOI CMOS technology.
• High Piezoelectric Properties In LiNbO3 Transferred Layer By The Smart Cut™ Technology For Ultra Wide Band BAW Filter Applications. J.-S. Moulet, et al. (Soitec, Leti)
  For the first time, HBAR resonators based on monocrystalline films of LiNbO3 fabricated using the Smart Cut™ technology were processed and characterized between 1 and 4 GHz, with results far superior to those obtained with traditional AlN material. This confirms the interest of this technology for ultra wide band BAW filters.
• Experimental Study on Quasi-Ballistic Transport in Silicon Nanowire Transistors and the Impact of Self-Heating Effects. R. Wang, et al. (Peking U., Samsung)
  This paper investigates ballistic efficiency and self-heating effects in GAA silicon nanowire transistors (SNWTs). It is experimentally found that, even if the SNWT is fabricated on bulk-Si substrate, the self-heating effect is worse than SOI devices.
• Demonstration of Highly Scaled FinFET SRAM Cells with High-k /Metal Gate and Investigation of Characteristic Variability for the 32 nm Node and Beyond. H. Kawasaki, et al  (Toshiba, IBM, Freescale, AMD)
  Researchers fabricated highly scaled FinFET SRAM cells, with area down to 0.128 m2, using high-k dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, mainly caused by heavy doping into the channel region.
• Impact of Strain on ESD Robustness of FinFET Devices. A. Griffoni, et al  (IMEC, U. Padova, Infineon, LAAS/CNRS, Texas Instruments)
  Researchers found that strain improves the ESD robustness up to 30% in multi-fin FinFETs.
• Atomistic Modeling of Impurity Ion Implantation in Ultra-Thin-Body Si Devices. L. Pelaz, et al  (U. Valladolid, NXP-TSMC, IMEC, Philips Research Labs)
  Source/drain formation in ultra-thin body devices by conventional ion implantation is analyzed using atomistic simulation. The conclusions of the atomistic modeling are verified by a novel characterization methodology and electrical analysis.
• Multi-Gate Vibrating-Body Field Effect Transistors (VB-FETs). D. Grogg, et al (École Polytechnique Fédérale de Lausanne)
  This paper reports on the design, fabrication and detailed characteristics of multi-gate vibrating-body field effect t ransistors (VB-FETs).  For the first time, the researchers experimentally demonstrate an active MEM resonator concept, with built-in amplification, which has a negative resistance of -30 Ohms, enabling the possibility of building an oscillator without any sustaining amplifier, thus reducing the power consumption and oscillator size.
• Sub-20 nm Gate Length FinFET Design: Can High-k Spacers Make a Difference? A.B. Sachid, et al (Indian Institute of Technology Bombay, Infineon)
  The authors present a novel device design methodology for the 45 nm technology node and below, for undoped underlapped FinFETs with high-kappa spacers to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped FinFETs.
• Transport-Based Dopant Metrology In Advanced FinFETs. G.P. Lansbergen, et al (Delft TU, Purdue U., U. Melbourne, IMEC)
  Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. The authors correlated the impurity’s chemical species and determined their concentration, local electric field and depth below the Si/SiO₂ interface, demonstrating a new approach to atomistic impurity metrology and confirming the assumption of tunneling through individual impurity quantum states.
• Novel Si-Based Nanowire Devices: Will they Serve Ultimate MOSFETs Scaling or Ultimate Hybrid Integration? (Invited)  T. Ernst, et al  (Leti)
  Since both CMOS scaling and NEMS sensor devices scaling converge to the same type of sub-100 nm objects, the authors explain how this opens the door to chips integrating both complex signal treatment and very highly sensitive sensing functionalities.
• 15nm-Diameter 3D Stacked Nanowires with Independent Gates Operation: ФFET. C. Dupre, et al (Leti, IMEP-LAHC, INPG-MINATEC, STMicroelectronics)
  The authors report the first 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.
• Enhancing SRAM Cell Performance by Using Independent Double-Gate FinFET. K. Endo, et al (National Institute of Advanced Industrial Science and Technology Tsukuba)
  The authors have successfully fabricated SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs and investigated the performance. They demonstrated both a reduction of leakage current and an enhancement of read and write noise margins.