San Franciso, February 2009
ISSCC is the foremost forum for presentation of advances in solid-state circuits and systems-on-a-chip.
- A 4-Side Tileable Back-Illuminated 3D-Integrated Mpixel CMOS Image Sensor. V. Suntharalingam, et al. (MIT Lincoln Labs, Irvine Sensors, Forza Silicon)
The paper presents a 3D-integrated back-illuminated (BSI) 1Mpixel CMOS image sensor tile for surveillance and astronomy. It includes a stack of 2×32-channel vertically integrated ADC chips, and requires 13.4μm of silicon perimeter to the pixel array. The tile and system connector design supports 4-side abuttability and burst data rates of 1Mpixel in 1ms. The first layer of the 3D-integrated 1Mpixel CMOS image sensor has photodiodes with 100% fill factor and is connected to a second layer consisting of SOI-CMOS pixel readout and selection circuitry. The next layers provide the digital system interface and serve as a mechanical support to the thinned imager. The butting gap is only 3 pixels (25μm) wide by design.
- A 5.4mW 0.0035mm2 0.48psrms-Jitter 0.8-to-5GHz Non-PLL/DLL All-Digital Phase Generator/Rotator in 45nm SOI CMOS. K-H. Kim, et al. (IBM)
A non-PLL/DLL all-digital phase generator/rotator is realized in 45nm SOI CMOS. The circuit accepts 2 input phases plus interpolator controls and produces 4 output phases; it also supports relative I/Q adjustment for CDR applications. The 0.0035mm2 circuit operates with phase error within 5° over a 0.8-to-5GHz range. At 5GHz, jitter is 0.48psrms, and the chip consumes 5.4mW from a 0.9V supply excluding the I/O buffers.
- An Array of 4 Complementary LC-VCOs with 51.4% W-Band Coverage in 32nm SOI CMOS. D. Kim, et al. (IBM, Qualcomm)
In order to provide wide range of oscillation frequencies in 100GHz band, an array of four switchable LC-VCOs, implemented in 32nm SOI CMOS. The VCOs cover 51.4% of W-band, occupy 40×35μm2 and are scalable for an array implementation in nanometer SoC.
- A sub-1V Bandgap Voltage Reference in 32nm FinFET Technology. A-J. Annema, et al. (U. Twente, NXP)
A sub-1V bandgap reference circuit is implemented in 32nm SOI FinFET technology, introducing an architecture that minimizes the total required resistor value. The circuit operates correctly for supply voltages above 0.9V with a supply current of 14μA at room temperature. This design is interesting both because of the use of a lubistor as the bandgap diode element as well as a unique way the PTAT and CTAT voltages are combined via matched OTAs.
- A 460W Class-D Output Stage with Adaptive Gate Drive. M. Berkhout (NXP)
A compact 460W audio amplifier with low EMI is integrated on SOI CMOS. The Class-D output stage operating from an 85V supply is realized in an SOI-based BCD process. The output stage uses an adaptive gate driver that adjusts the speed of charging and discharging of the gates of the power MOSFETs depending on their terminal voltages. Measurements show smooth transitions at high output currents and output power is 460W at 10% THD.
- A 2ns-Read-Latency 4Mb Embedded Floating Body Memory Macro in 45nm SOI Technology. A. P. Singh, et al. (Innovative Silicon, AMD)
The paper describes a novel 4Mb DRAM memory macro using a floating-body SOI bitcell that is compatible with an SOI logic process. The macro features a single-ended capacitively coupled sense amplifier that results in 2ns read latency and a 4ns random cycle. The capacitorless memory cell achieves a macro density of 0.21mm2 /Mb. The embedded memory macro is developed for high-performance microprocessors, using a single-transistor floating-body cell. Eight 4Mb macros are incorporated on a test-chip fabricated in a 45nm SOI logic process. Silicon measurements confirm 2ns read latency with a memory-macro operating window of 0.5V.