MEMS in thin film SOI


MEMS in thin film SOI

SOI is major contender for heterogeneous applications.

The advantages of SOI technology for building thin film sensors on membranes as well as three-dimensional (3D) surface micromachined sensors and actuators have been demonstrated over these last years. The flatness and robustness of the thin membrane as well as the self-assembling of out-of-plane 3D microstructures rely on the chemical release of the microstructures and on the control of the residual stresses building up in multilayered structures undergoing a complete thermal process.

In an SOI wafer configuration, the structural and sacrificial layers are directly available in the system. Indeed, the buried oxide (BOX) is an excellent etch-stop layer when micromachining the bulk silicon wafer from the backside and the top thin monocrystalline silicon layer presents excellent intrinsic mechanical properties for building robust and reliable surface micromachined sensors.

SEM picture of a co-integrated 3D MEMS capacitive sensor with its differential associated SOI CMOS circuit, ring oscillators with output buffers.

Moreover, assuring a CMOS-compatible MEMS process, passive (piezoresistors) or active (MOS transistors and CMOS circuits) transducers can be directly integrated into the released thin monocrystalline silicon of the SOI wafer. Gas [1, 2], flow [3] and pressure [4] sensors with their associated SOI CMOS electronics beside or even on top of the flat and slightly tensile released membrane have been successfully fabricated and characterized.

The out-of-plane deflection of released multilayered structures made of both elastic and plastic thin films results from the thermal expansion coefficient mismatches between the layers and from the plastic flow of the metallic layers [5].

In contrast with techniques presented in the literature for the fabrication of 3D MEMS, the present process requires fabrication steps and machines fully compatible with a classical CMOS process and available in standard CMOS foundries. 3D thermal and flow sensors based on capacitive sensing co-integrated with thin SOI CMOS circuitry demonstrate the potential of this concept.

[1] J. Laconte, C. Dupont, D. Flandre and J.-P. Raskin, “SOI CMOS compatible low-power microheater optimization for the fabrication of smart gas sensors”, IEEE Sensors Journal, vol. 4, no. 5, pp. 670-680, October 2004.

[2] P. Ivanov, J. Laconte, J.-P. Raskin, M. Stankova, E. Sotter, E. Llobet, X. Vilanova, D. Flandre and X. Correig, “SOI-CMOS compatible low-power gas sensors using sputtered and drop-coated metal-oxide active layers”, Journal of Microsystem Technologies, vol. 12, no. 1-2, pp. 160-168, December 2005.

[3] J. Laconte, B. Rue, J.-P. Raskin and D. Flandre, “Fully CMOS-SOI compatible low-power directional flow sensor”, IEEE Sensors 2004 – The Third IEEE International Conference on Sensors, Vienna, Austria, October 24-27, 2004, pp. 864-867.

[4] B. Olbrechts, B. Rue, J. Suski, D. Flandre and J.-P. Raskin, “Characterization of FD SOI devices and VCO’s on ONO membranes under pressure”, Solid-State Electronics, vol. 51, pp. 1129-1237, 2007.

[5] F. Iker, N. Andre, T. Pardoen and J.-P. Raskin, “Three-dimensional self-assembled sensors in thin film SOI technology”, IEEE Journal of MicroElectroMechanical Systems, vol. 15, no. 6, pp. 1687-1697, December 2006.

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