Leti, Soitec and ST have discovered the sources of threshold voltage variation in undoped, ultrathin FD-SOI architectures.
Fig. 1 TEM picture of the transistor architecture studied.
Fig. 2 This figure shows the σVt, DIBL as a function of TSi measured by ellipsometry. Vt fluctuations due to σL and the DIBL are minimized by thinning TSi.
Fig. 3 This figure shows the σVt for a new process. By minimizing the short channel effects, σVt of short L can be aligned with σVt of long channel FETs.
Fig. 4 This graph summarized the various factors responsible for the local Vt variability in undoped 8.5nm-TSi FDSOI devices with a HfO2/TiN gate stack.
At the most recent IEDM conference, researchers from Leti, Soitec and STMicroelectronics presented a paper entitled, “High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding” (O. Weber et al, IEDM 2008).
The paper highlights the following breakthroughs:
- Sources responsible for local and inter-die threshold voltage (Vt ) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time.
- Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local Vt variability.
- Prior to this paper, some in the industry had postulated that in the most advanced SOI transistors, variation in the thickness of the top silicon layer (TSi ) contributed to Vt variation. As described in this paper, it is found that SOI thickness (TSi ) variations have a negligible impact down to TSi = 7nm.
- TSi scaling is shown to limit both local and inter-die Vt variability induced by gate length fluctuations.
- The highest matching performance ever reported for 25nm gate length MOSFETs is achieved (AVt=0.95mV.μm), demonstrating the effectiveness of the undoped, ultra-thin FDSOI architecture in terms of Vt variability control.