At the most basic level, a transistor is turned on if the gate voltage is higher than the threshold voltage. That makes reducing variability in threshold voltage (which can be abbreviated as either σVth or σVt) critical.
Further compounding the problem, σVth tends to increase with scaling, thereby preventing the reduction of supply voltage and standby leakage current. This is a major – if not the major – challenge for leading-edge CMOS.
In scaled bulk CMOS, random doping fluctuation (RDF) is a major cause of increasing σVth.
It is widely recognized that with fully-depleted (FD) SOI, double gate or FinFETs with low (doping) dose channel structures can eliminate RDF, thus reducing variability.
In these papers presented by Hitachi and Leti at the most recent IEDM conference, significant breakthroughs were presented in understanding and reducing σVth in FD-SOI architectures.