The joint survey we did with the GSA last year clearly indicated that lowering power is a primary driver for designers considering SOI-based solutions. Therefore, our 2009 focus is putting a particular emphasis on IP and outreach efforts highlighting the green, energy-saving advantages of SOI.
Our dedicated IP committee is working hard to close the remaining IP gaps. Concurrently, various members are collaborating to demonstrate the performance of key IP on SOI and solidify the ecosystem around the foundries.
Following on the success of last year’s design clinics in Taiwan and the US, we’ve got three more planned for the US and India. You’ll also find us at strategic industry events.
See the website for information on how to join: www.soiconsortium.org
Now joining the membership roster is: IMEC
As indicated in our ’09 plan, the Consortium is increasing the focus on SOI’s power-saving advantages. The power efficiency benefits of SOI are widely valued. However, much of SOI’s current traction is based on the success of designs that leveraged its high-performance advantages.
The power-saving advantages of SOI represent a huge opportunity for us. Given our current market environment, the recent growth of the “green movement”, and the premium now being placed on reducing power consumption in most applications, we can seize this moment to capitalize on SOI’s ongoing record of green, low-power benefits.
SOI is a “green technology”, offering 30-40% savings in semiconductor power consumption compared to traditional approaches. SOI substrates also provide a compelling foundation for producing ultra low-power semiconductor solutions for today’s mobile and power conscious society.
Our members’ expertise and participation will ensure that the pieces are in place and the word gets out.
The IP team is actively working on contacting IP companies that can support SOI. A list will soon be available on our web site for any potential user.
Two white papers that describe the SOI design process for engineers considering the technology are now in the works. The goal is to put an end to the myth that SOI design is inherently difficult.
Additionally the IP team is working on an “SOI fact sheet”, a basic document to answer the key, fundamental questions about SOI—its advantages and capabilities—for a wide, technical audience.
Since last year, we have been rolling out “The SOI Implementation Guide,” a series of white papers and presentations to drive common understanding of the value and challenges of SOI. Most recently we released a series of presentations that are part of a course offered by the Consortium focusing on RF/analog & mixed-signal topics.
The most recent releases include:
A special thanks to Dr. Denis Flandre from the Université Catholique de Louvain for these recent contributions.
If your company is a member of the Consortium, you can get a copy of these guides under the myConsortium header on our website. This is a password-protected area: if you are eligible but don’t yet have a password, use the “contact us” button. Make sure to access to them at “myConsortium” on the web site when you get the alert.
We have recently launched a FinFET-on-SOI technical evaluation project. The goal of the project is to assess and compare SOI and bulk for FinFET architectures.
A multi-company, cross-discipline team will provide an assessment of the challenges of developing and manufacturing FinFETs. The team comprises senior technologists from independent device manufacturers, foundry, equipment manufacturers, research institutes and academia.
The goal is to provide an in-depth understanding of the various tradeoffs and to offer direction in this key technology area.
We are evaluating the technology capabilities and manufacturability from the perspective of technology readiness, variability, complexity comparisons, as well as power and performance comparisons.
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