2009 Silicon Nanoelectronics Workshop
Posted date : Jul 30, 2009


13-14 June 2009, Kyoto, Japan

The workshop focuses on silicon-related nanoelectronics, to bridge a gap between the Si nano-technology and the “real” VLSI world. It is sponsored by the Japan Society of Applied Physics and the IEEE EDS. Click here for a pdf of the full program.

  • The Impact of SOI Thickness on Device Characteristic and Reliability for FUSI CMOSFET with CESL Strain Technology
    C.-C. Wang, et al. (National U. Kaohsiung, National Tsing-Hua U., UMC)
  • Minimization of Gate-Induced Drain Leakage (GIDL) for Low Standby Power in 20 nm Level SOI 4-T FinFETs by controlling Underlap Lengths
    S. Cho, et al. (Seoul National U., AIST)
  • Effect of δ-function-like Boron Charge Sheet on p-channel Ultra-Thin SOI MOSFETs
    M. Kawachi1, et al. (Akita University, NTT Basic Research Laboratories)
  • Spectroscopic Response of SOI Photodiode with Gold Line-and-Space Surface Plasmon Antenna
    H. Satoh, et al. (Shizuoka U.)
  • Impact of TiN Gate Thickness in Advanced FD SOI MOSFETs
    L. P-Nguyen, et al. (IMEP-INPG, CEA-Leti-Minatech, ST Microelectronics)
  • Transport Optimization with Width Dependence of 3D-Stacked GAA Silicon Nanowire FET with High-k/Metal Gate Stack
    K. Tachi, et al. (CEA-Leti-Minatech, 2IMEP-LAHC INPG-Minatech, Tokyo Institute of Technology)

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