How IBM’s Cu-45HP ASIC leverages SOI for an overall lowering of power.
Initiatives for a smarter and greener planet are creating ubiquitous demand for higher intelligence, integration and performance at the lowest possible power. New regulations, such as Energy Star, are being contemplated for many industries.
Application and system requirements are prompting a dramatic shift in customer priorities. Power has become a prominent consideration in design of electronic components and systems.
Historically, CMOS scaling was the primary path to performance and integration. Advanced BEOL materials augmented the device scaling. However, the increase in power density with each technology node has created a power distribution and cooling challenge.
Innovation now dominates power and performance gains between technology generations. Going forward, device and material innovations will be needed to meet the challenges of power and performance at component and system levels, alike.
SOI is one of the material innovations employed in IBM’s Cu-45HP ASIC design system. SOI offers superior isolation for circuits and devices (see Figure 1).
Superior isolation results in reduced variability of device parameters such as threshold-voltage, current drive, and capacitance. Reduced variability results in lower capacitance and allows lowering of supply voltage for an overall lowering of power.
Circuit isolation further eliminates device failures due to latch-up. Due to the smaller bulk region, or body, between source and drain, soft error rate is reduced by many fold (5-7x).
The floating body also contributes in faster CMOS switching and hence higher performance. SOI can also support device operation at higher junction temperature than normal due to lower leakage-current susceptibility.
SOI enables compact integration of IP blocks (e.g. eSRAM, eDRAM and SerDes) to achieve superior density and power. Deep-trench decoupling capacitors offer a significant area and leakage advantage in mitigating effects of simultaneous switching noise.
Flexible on-chip power management elements, featuring multi-threshold libraries and voltage islands, support a broad range of voltages while enabling area, power and performance trade-offs.
SOI does not change the chip design flow. VHDL & Verilog remain the same; physical layout architecture remains the same. IBM’s time-tested ASIC design methodology and extensive IP library can help get even the most complex designs right the first time.
Lower component power can further translate into cost advantages such as lower packaging costs, lower system cooling cost and lower power supply cost.
IBM’s SOI based Cu-45HP ASIC design system is ready to meet demands of a wide range of high-performance and low-power applications across a broad cross-section of markets (see Figure 2).
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