18 -20 May 2009, Austin, TX
Sponsored by the IEEE Central Texas Section and the Japan Society of Applied Physics, ICICDT provides a forum for engineers, researchers, scientists, professors and students to cross this boundaries between design and processes.
- Robust multi-VT 4T SRAM cell in 45nm thin BOx fully-depleted SOI technology with ground plane
J.-P. Noel, et al. (CEA-Leti-Minatec)
This paper proposes a new compact, robust and low leakage 4T SRAM cell. It is based on an original concept of multi-VT thin buried oxide (BOx) fully-depleted FD-SOI MOSFETs with ground plane (GP) in 45nm technology node, and is 16% smaller than the smallest 6T SRAM cell reported in 45nm Bulk technology. Moreover, the proposed cell displays a good manufacturability. It is a cost saving process because it requires only one GP doping, no substrate contact at the cell level and is based on a conventional FD-SOI process flow.
- The tunnel source MOSFET: A novel asymmetric device solution for ultra-low power applications
N. Venkatagirish, et al. (UCLA)
A novel asymmetric Tunneling Source SOI MOSFET is proposed in this paper. The main feature of this device is the concept of gate controlled carrier injection through band-to-band tunneling at the source junction. It also possesses excellent immunity against short channel effects, which improves scalability into the sub-50nm regime and makes it an attractive candidate for low power digital and analog operations. (Read the “Professor’s Perspective” article by UCLA Professor Jason Woo in this edition of ASN for a more complete account.)
- Future of planar self-aligned block oxide based MOSFET technology
Jyi-Tsong Lin, et al. (National Sun Yat-Sen U.)
This paper examines the current-voltage (IV) and capacitance-voltage (CV) characteristics of self-aligned (SA), planar block oxide (BO) MOSFETs using technology computer-aided design (TCAD) tools. For the first time, a comparison of the different types of BO MOSFETs, such as FDSOI FET with BO (bFDSOI), silicon-on-partial-insulator (SPI) FET with BO (bSPI), source/drain (S/D)-tied bFDSOI-FET, and multi-substrate contact (MSC) FET, is studied through numerical simulations.
- QorIQ P4080 Communications Processor design in 45nm SOI
Greg Bartlett (Freescale)
The QorIQ P4080 processor, the first product offered in the Freescale QorIQ P4 platform series, delivers industry leading performance under 30-watts. It combines eight Power Architecture™ e500mc cores — operating at frequencies up to 1.5 GHz — with high-performance datapath acceleration logic, and network and peripheral bus interfaces. The design is in 45nm SOI technology to deliver high-performance, next-generation networking services in a very low power envelope. In addition to the applications features of the P4080 Communications Processors, the design challenges associated with bringing this sophisticated product to the market are also be described.