Low Power Design: Fast & Green
Posted date : Jul 30, 2009

SOI helps create faster chips that consume less power.

Speed and area used to be the primary factors considered by chip designers. Performance requirements were established, and the power consumption required to achieve them was just another detail. In recent years, chip designers hit a wall. And sustainability moved to the forefront of industry.

Achieving higher chip speeds demanded increased power, but chips ran too hot for conventional cooling methods and drew exorbitant amounts of energy. An advanced technology known as SOI now makes new levels of chip performance and efficiency possible. SOI allows chip designers to create faster chips that are “greener” by using less power.

More speed, same power; same speed, less power

The relationship between chip performance and power consumption is fairly linear. While SOI cannot eliminate the correlation between performance and power usage, it can significantly shift the ratio between the two factors.

Layering silicon on insulator substrate as opposed to conventional bulk silicon substrate reduces parasitic device capacitance, which increases performance while decreasing power consumption. This offers a clear environmental benefit, as an SOI chip generates less heat, consumes less power, and has a lower overall operating cost.

What about the design?

Using an SOI substrate affects the design process in two areas: TCAD and low-power strategies.

TCAD (technology CAD) models both semiconductor fabrication and device behavior.

TCAD tools must understand the SOI manufacturing “recipe” and performance of transistors, which are different than those of bulk substrate. Foundries must also provide SOI design rules for tools such as design rule checking.

Simply porting a design onto SOI doesn’t provide the optimal power savings that come with an accompanying low-power design strategy. Clock-gating, multi-voltage islands, and dynamic voltage & frequency scaling are modern techniques for creating a chip designed to use less power.

The solution from Synopsys called “Eclypse” offers a complete flow, based on IEEE standard 1801, to create optimal low-power chip designs. With Eclypse, SOI chips can be designed using the same advanced tools and methods used for conventional chips.

The combination of SOI technology and the Eclypse low-power design solution is synergistic sustainability in action.

An SOI chip generates less heat, consumes less power, and has a lower overall operating cost.

A 200mm SOI wafer that was manufactured on a standard CMOS fabrication line. (Courtesy: Alexander A. Trusov)

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