Symposia on VLSI Technology and Circuits
Posted date : Jul 30, 2009

www.vlsisymposium.org

15-18 June 2009, Kyoto, Japan

The VLSI Symposia on technology and circuits are amongst the most influential in the semiconductor industry. Click here for links to all the abstracts for the Technology Symposium.

• High Hole Mobility in Multiple Silicon Nanowire Gate-All-Around pMOSFETs on (110) SOI
  J. Chen, et al. (U. Tokyo)
  A systematic study on hole mobility in gate-all-around (GAA) multiple Si nanowire (NW) pFETs on (110) SOI is presented for the first time. [110]-NWs show high mobility, 2.4x enhancement over universal (100) mobility, even in high Ninv region and in narrow (25nm) NWs. Furthermore, effects of uniaxial tensile stress are also investigated, indicating that [110] direction uniaxial stress is effective to modulate hole mobility in NWs.
• High Performance 32nm SOI CMOS with Highk/ Metal Gate and 0.149μm² SRAM and Ultra Low-k Back End with Eleven Levels of Copper
  B. Greene, et al. (IBM, AMD, Freescale)
  This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 μm2. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. For the first time, it is demonstrated that SOI maintains performance benefits over bulk silicon in high-k/metal gate and 32nm ground rules.
• Characteristics of sub 5nm Tri-Gate Nanowire MOSFETs with Single and Poly Si Channels in SOI Structure
  S.D. Suk, et al. (Samsung)
  A sub 5nm tri-gate nanowire MOSFET is successfully developed with good uniformity by using conventional technology in the SOI structure.
• GeOI and SOI 3D Monolithic Cell Integrations for High Density Applications
  P. Batude, et al. (CEA-Leti, STMicroelectronics)
  In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process of the top GeOI and SOI MOSFETs leads to well-behaved characteristics and allows preservation of bottom FETs performance. Processing CMOS on each layer leads to an average 40% density improvement as compared to 2D standard layout.
• Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Featuring Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain
  K. Cheng, et al. (IBM)
  A novel integration scheme is presented to solve multiple issues for ETSOI technology. Remarkable drive currents and excellent electrostatics are simultaneously achieved with gate length down to 25nm, indicating ETSOI devices are suitable for 22-nm node and beyond.
• Comprehensive Understanding of Surface Roughness Limited Mobility in Unstrained- and Strained-Si MOSFETs by Novel Characterization Scheme of Si/SiO2 Interface Roughness
  Y. Zhao, et al. (U. Tokyo, Hitachi)
  In this paper, a novel method to determine the surface roughness-limited mobilities of electrons and holes in MOSFETs directly from experimental data of MOS interface roughness is proposed and compared with experimental [data] with and without bi-axial tensile strain.
• Low Voltage (Vdd~0.6 V) SRAM Operation Achieved by Reduced Threshold Voltage Variability in SOTB (Silicon on Thin BOX)
  R. Tsuchiya, et al. (Hitachi)
  The authors successfully demonstrate a “silicon on thin BOX” (SOTB) 6T-SRAM with a 50-nm gate. The SOTB CMOS exhibits superior reliability and noise performance. These characteristics indicate robust properties for future industrial high performance and low power LSIs.
• Highly Scalable Z-RAM with Remarkably Long Data Retention for DRAM Application
  S. Jang, et al. (Hynix, Innovative Silicon)
  The operating characteristics and retention times of floating body cells and arrays using Z-RAM technology fabricated on a 50nm DRAM process are presented. For the first time, data retention time longer than 8s at 93oC and 1.6V wide programming window are obtained on floating body cells as small as 54nm x 54nm. These results demonstrate the suitability of floating body memories for DRAM applications. These improvements were obtained through optimization of DRAM technology such as junction engineering, thermal treatments, and improved passivation processes.