Implementing the 45nm SOI ARM11
Posted date : Dec 4, 2009

The mobile app chip’s 40% power saving was achieved without any major rework in design methodology.

At the IEEE SOI Conference, ARM announced the results from a 45nm SOI test chip. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations.

The goal was to demonstrate the power savings in a real silicon implementation with a well-known, industry-standard core, in an apples-to-apples comparison of 45nm SOI high-performance technology with bulk CMOS 45nm low-power (LP) technology.

The results confirm SOI technology is a viable alternative to traditional bulk process technology when designing low-power processors for high-performance consumer devices and mobile applications.

The 45nm high-performance SOI technology can provide up to 40% power savings and a 7% circuit area reduction compared to bulk CMOS low-power (LP) technology, operating at the same speed. This same implementation also demonstrated 20% higher operating frequency capability over bulk while saving 30% in total power in specific test applications.

Typical app, standard tools

For this demonstration, we chose a typical design point for an ARM11 implementation in a mobile phone application. The design was implemented using ARM and IBM standard SOI libraries and leading EDA tools.

The performance target was a 500Mhz design point at <100mW total power, at a slow (SS) process corner, 125ºC, and minimum voltage of the technology.

The same EDA flow, synthesis and place and route (P&R) scripts were used to design the 45SOI and 45LP test chips using 8 metal layers. Most of the tools used for implementation were from Synopsys, like Design Compiler® for synthesis, IC Compiler ICC for place and route, StarRC™ for extraction and PrimeTime® SI for static timing analysis (STA).

Design methodology

The history effect is one of the unique effects in SOI technology affecting the cell delays, which becomes a function of the switching history of device. To model the history effect for a particular power/voltage/temperature (PVT), there are two libraries, max and min to define maximum and minimum propagation delay. Until the clock tree is built, the operating condition of the chip is defined with worst case libraries of each PVT: max library for slow-process, low-voltage, high-temperature; and min library for fast-process, high-voltage, low-temperature.

From Clock Tree Synthesis (CTS) onwards, two operating conditions are defined,  one each for setup and hold using max and min library variants of each PVT.

For setup, the max and min library for slow-process, low-voltage, high-temperature is used: max library is used for launch path; min library is used for capture path.

For hold, the max and min library for fast-process, high-voltage, low-temperature is used: min library is used for launch path; max library is used for capture path.

To optimize the design in two scenarios, the multi-corner, multi-mode (MCMM) feature of the Place and Route tool needs to be used.

90% of the ground rules are same between bulk and SOI CMOS. Apart from the history effect, the other major affect is that SOI does not require a TAP cell.

SOI effects have posed some unique challenges for implementation and signoff. All these effects are manageable and shifting the process from bulk CMOS to SOI requires only minor changes in the implementation methodology.

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