Increased expectations, drastic reductions
Posted date : Dec 4, 2009

Ultra-low-power design has long been confined to watches, RFID or biomedical niches. But new horizons are opening with the increasing expectations for mobile and ubiquitous devices, and with scaling enabling system-on-chips to meet lower power targets while maintaining performance.

The ULP diode consists in a pair of source-connected n- and p-MOSFETs with each drain connected to the other’s gate. The I-V curve in forward operation features high drive current, while in reverse, the voltage drop VD being equal to the sum of a negative Vgs on the nMOS and a positive on the pMOS, the common off current settles below the 0-Vgs value, yielding a negative resistance characteristic for larger reverse VD and eventually, extremely low leakage current.

Power consumption results from dynamic switching and static or stand-by leakage. Dynamic switching can be mitigated by lowering total load capacitance or supply voltage, which SOI is obviously good at.  Stand-by leakage is becoming dominant for low-duty cycle operation (such as in SRAM) and calls for a drastic reduction of the off current (or Ioff). But this can’t be at the expense of functional performance, e.g. by significantly increasing the threshold voltage.

Pushing Ioff

In conventional CMOS design, Ioff is constrained by the zero gate-to-source voltage (or Vgs) level. To get below this limit, at UCL we have experimented with new ultra-low-power (or ULP) design techniques in which the MOSFET can be automatically biased at negative Vgs in stand-by mode, thereby pushing Ioff towards its physical limits.

Our novel basic block consists of only two transistors : an nMOS and a pMOS, but as opposed to a standard CMOS inverter, the nMOS is on top of the pMOS (see figure).

Playing with gate and drain connections, we have created a family of ULP blocks: a 2-terminal diode, a 3-terminal transistor and a voltage reference.

Record reductions

Implemented in SOI, our voltage reference shows a record power consumption of a few nanowatts(1) (nW) at 25°C in fully-depleted (FD) SOI. By comparison, consider that power consumption typically runs well above 1µW for usual bandgap circuits. Furthermore, our design reduces die area by more than 100x.

Our ULP diode was used in partially depleted (PD) SOI to design a novel SRAM. It posted a record reduction of static power consumption: down 50x when compared to 6T-SRAM, with no speed penalty and even improved static noise margins. Other logic blocks such as adders and MTCMOS gates have been demonstrated.

In the analog field, the ULP diode has been used as a low-leakage component in SOI rectifiers, charge-pumps, energy harvesting and power management — all with unequaled efficiency.
SOI is thus the technology of choice for our R&D on Ultra-Low-Power applications.

(1) A nanowatt is one thousand millionth — also known as a billionth (10-9) —  of a watt

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