Reports & Papers
Posted date : Dec 4, 2009

Floating Body Effects: Just the Facts

For designers who’ve never worked in SOI, rumors surrounding the “floating body effect” might make SOI  seem like too much of a challenge. A paper freely available on the SOI Industry Consortium website entitled “De-myth-tifying” the SOI Floating Body Effect by Bob Ulicki and Herb Reiter puts an end to any lingering misconceptions.

  • As the authors point out, myths that Floating Body Effects in PD-SOI devices will cause serious performance issues or catastrophic functional problems are based on a simple lack of understanding of what is happening to body voltages during both startup and operating modes.
  • Once the basics of charge variation are understood, designers will realize that all they have to do is a bit more timing analysis using existing STA procedures. The standard tools from the major EDA Tool vendors render the Floating Body Effect transparent to the designer.
  • This paper is the first in a series of SOI topics showing why the reality of physics speaks for much broader deployment of SOI. Other papers will also examine why economics will push SOI cost benefits for scaling through 22nm and beyond.

SOI Design Fundamentals

Engineering services company and Consortium member Infotech Enterprises has contributed an excellent white paper entitled Silicon On Insulator (SOI) Implementation. Author Narayana Murty Kodeti takes the designer through SOI basics, covering design specificities and techniques, and concluding with an ASIC design strategy. The paper is now freely available on the consortium website.

The SOI Consortium-sponsored FinFET study made the cover of the November 2009 issue of SST magazine.

SST Cover Story:
FinFET – SOI vs. Bulk at 22nm

The SOI Consortium-sponsored FinFET study made the cover of the November 2009 issue of SST magazine.

The study was the cover story of the November 2009 issue of SST magazine.

It evaluated performance, process variability, and cost differences between FinFETs fabricated with junction isolation on bulk silicon wafers, and FinFETs fabricated on SOI wafers. The analysis shows that fabrication on bulk and SOI wafers is for all practical purposes equivalent in performance and cost. However, bulk-based FinFETs are much more challenging to manufacture due to increased process variability.

The Growing Implementation Guide

The ninth chapter of the ongoing Implementation Guide has been posted. Contributed by Professor Denis Flandre, who heads up the microelectronics lab at the Université Catholique de Louvain, Design of SOI VCO/PLL Demos covers circuit examples of  VCO, CCO, PLL, and DLL devices. It includes design suggestions, optimization tips, comparisons of PD and FD SOI and case studies.

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