SOI’s seven ESD design advantages
Posted date : Dec 4, 2009

SOI technology has some natural advantages in electrostatic discharge (ESD) design. At first glance, many engineers believe that it is a disadvantage to provide ESD design on SOI compared to bulk silicon technology. But, after working with SOI , there are many advantages.

Dr. Voldman’s latest book, ESD: Failure Mechanisms and Models (©2009), is the fifth in his series on ESD-related design issues. (Courtesy: John Wiley & Sons)

1 – A first advantage is elimination of parasitic elements that can lead to ESD failure mechanisms. One of the difficulties in bulk CMOS design is the parasitic “turn-on” of lateral npn devices formed between n+ diffusion, wells, and guard rings; in SOI, parasitic elements are not present.

2 – A second advantage is the elimination for a requirement of guard rings. Guard rings separate ESD elements from I/O elements, I/O to I/O, I/O to internal circuits, and function-to-function; in SOI, all these issues are irrelevant. Additionally, in SOI, no additional space is wasted.

3 – A third advantage is elimination of CMOS latchup. 

4 – A fourth advantage is the presence of the buried oxide (BOX) provides de-coupling of the substrate from the p- epitaxial region. One of the largest problems in bulk CMOS ESD design is that in multi-finger MOSFET structures, each of the MOSFET fingers is at a different spacing relative to the substrate contact. In bulk CMOS, as the MOSFET drain voltage increases, the IR drop relative to each finger to the substrate contact is not equal; this effect leads to non-uniform turn-on of the MOSFET and lower ESD results. The beauty of SOI technology: the de-coupling from a body contact allows for uniform current flow in each MOSFET finger. This de-coupling effect allows for improved ESD current uniformity in diodes, and MOSFET-based ESD structures. Today, there is evidence that SOI defined FinFET structures demonstrate improved ESD compared to planar bulk MOSFETs.

5 – A fifth advantage is the presence of the BOX for dynamic MOS (DTMOS) threshold effects and DTMOS ESD networks.

6 – A sixth advantage is the presence of the BOX allows for design symmetry for both  ESD pulse polarities.

7 – A seventh advantage for SOI is the charged device model (CDM) events. In SOI, the floating body and de-coupling from the substrate avoids CDM failures in CMOS inverters and internal circuitry.

Can you get great ESD results in SOI? Yes, we can.

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