Fully Depleted (FD) SOI for the Next Generation

FD-SOI is making the move towards industrialization. In this issue of ASN, experts from IBM, ST, Hitachi, Leti and Soitec detail their approaches.

What is it ?

In planar FD-SOI (as opposed to the verticality of FinFETs), CMOS transistors are built into an ultra-thin layer of silicon over a Buried Oxide (BOx) (which can optionally be extremely thin, too). This makes them Ultra-Thin Body Devices, with unique characteristics.

Why use it?

Planar FD-SOI addresses the major scaling challenges beyond the 28nm node:

Lowering supply voltage (VDD – hence power consumption per device) while boosting the dynamic performance;
Stopping – even better, reversing – the dramatic increase of variability in transistor characteristics;
Continuing to shrink transistor dimensions while limiting leakage and other unwanted short channel effects.

As a result, the unique properties of fully depleted devices – combined with the simplicity of a planar FD-SOI process and optimized wafer costs – put FD-SOI in the cost-of-ownership “sweet spot” for finished chips.

For which applications?

The primary application targets of FD-SOI are low power Systems-on-Chips (SOCs), including those that need to combine demanding dynamic performance with low (static and dynamic) power consumption. That covers markets such as: Cellular Telecom, Mobile Internet Devices (Smartphones, Tablets, Netbooks), Home and Mobile Multimedia, etc.

When will it be ready?

FD-SOI is a very serious candidate for mainstream technology at the 22/20nm low power node, which targets qualification around the end of 2012. Many extremely encouraging results have already been reported by different technology R&D teams, with recent updates at IEDM in December 2009. More broadly:

industrial wafers in line with the tight requirements of FD-SOI are available;
the fab toolset is the same as for bulk CMOS;
and the design flow is not disruptive.

See the SOI Industry Consortium website for an in-depth FAQ on FD-SOI.