FD-SOI is making the move towards industrialization. In this issue of ASN, experts from IBM, ST, Hitachi, Leti and Soitec detail their approaches.
In planar FD-SOI (as opposed to the verticality of FinFETs), CMOS transistors are built into an ultra-thin layer of silicon over a Buried Oxide (BOx) (which can optionally be extremely thin, too). This makes them Ultra-Thin Body Devices, with unique characteristics.
Planar FD-SOI addresses the major scaling challenges beyond the 28nm node:
As a result, the unique properties of fully depleted devices – combined with the simplicity of a planar FD-SOI process and optimized wafer costs – put FD-SOI in the cost-of-ownership “sweet spot” for finished chips.
The primary application targets of FD-SOI are low power Systems-on-Chips (SOCs), including those that need to combine demanding dynamic performance with low (static and dynamic) power consumption. That covers markets such as: Cellular Telecom, Mobile Internet Devices (Smartphones, Tablets, Netbooks), Home and Mobile Multimedia, etc.
FD-SOI is a very serious candidate for mainstream technology at the 22/20nm low power node, which targets qualification around the end of 2012. Many extremely encouraging results have already been reported by different technology R&D teams, with recent updates at IEDM in December 2009. More broadly: