SOI experts continue to join the prestigious list.
Thomas SKOTNICKI, a Fellow and Advanced Devices Program Director at STMicroelectronics, joins the list of IEEE Fellows “for contributions to development of metal-oxide semiconductor field effect transistor models and advanced semiconductor technologies”. His current focus is on low power/low variability for 32-nm and beyond CMOS, innovative device architectures, new memory concepts and cells, and the integration of new materials for CMOS.
Andrew MARSHALL has been named an IEEE Fellow “for contributions to process development and design of integrated circuits”. A Distinguished Member of the Technical Staff at Texas Instruments’ Technology Development organization, he provides analog, digital and RF support for advanced processes, including partially depleted SOI and FinFET fully depleted SOI. He is the co-author of SOI Design: Analog, Memory and Digital Techniques (Springer, 2001).
Paul DODD, a Sandia National Laboratories researcher, has been named an IEEE Fellow “for contributions to the understanding and simulation of single-event effects in microelectronics”. He has been involved in the development of Sandia’s radiation-hardened bulk and SOI CMOS technologies, the investigation of physical mechanisms responsible for device radiation response, and the computer simulation of radiation effects on microelectronics.
Yasuhisa OMURA, professor in the Department of Electrical and Electronic Engineering of Kansai University, was made an IEEE Fellow “for contributions of silicon on insulator devices technology, analysis, and modeling”. He has invented various SOI devices, and is currently working on device physics of ultimately miniaturized MOSFET/SOI, modeling for MOS device design, fluctuation physics and development of silicon photonic devices.
Dimitris IOANNOU, professor of electrical and computer engineering at George Mason University, has been made an IEEE Fellow “for contributions to reliability and characterization of silicon-on-insulator devices and materials”. He also discovered the opposite-channel based carrier-injection and an SOI flash memory cell. His current research interests are on performance and reliability issues of SOI CMOS devices and circuits.
Gary PATTON of IBM was elevated to IEEE Fellow “for contributions to silicon germanium heterojunction bipolar transistors”. He is currently vice president of IBM’s Semiconductor Research & Development Center. As such, he is responsible for the development of IBM’s entire portfolio of leading edge process and packaging technologies, including next generation SOI and bulk CMOS, embedded DRAM, SiGe BiCMOS and RF CMOS.
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