Key advances in transistor research start on SOI.
SOI has always been the substrate of choice to explore new silicon device concepts and structures. The full dielectric isolation of the silicon allows one to dismiss the sometimes complex junction isolation schemes used in bulk silicon. The possibility of making devices in thin silicon films has enabled a number of new operation modes such as: volume inversion, where the bulk of the silicon film is inverted; and accumulation-mode operation, in which the channel region has the same doping polarity as the source and drain.
It is only afterwards that bulk processes are devised to mimic the original SOI device: the bulk FinFET is a bulk silicon version of the DELTA device or the SOI FinFET; and the double-gate silicon-on-nothing device is a version of the gate-all-around FET that does not use SOI wafers.
Another key advantage of SOI is the possibility of fully depleting a device. This is obviously not possible in bulk silicon.
Fully depleted MOSFETs have long been known to be “ideal” transistors, featuring optimal subthreshold slope, optimal body effect, better current drive, transconductance and linearity than bulk transistors, and lower soft error rate. They also show lower leakage currents and threshold voltage variation when temperature is increased.
Yet, these devices have not yet been widely adopted by industry. Recent findings by Leti and other research groups show that transistor parameter variability can be reduced when using FD-SOI. This may be the trigger point that may convince the industry.
We can add to the picture the fact that “remote” or “virtual” doping can be achieved using the “back-gate mirror doping” technique, in which forming a doping profile in the substrate below a thin BOX is found to “induce” a similar doping profile in the thin-film SOI device above the BOX. This effect can be used to modulate the virtual doping concentration in channels that are, otherwise, lightly doped or undoped.
But there are also very exciting results at the other side of the doping concentration scale. The recently published junctionless transistor is a heavily doped silicon SOI nanowire pi-gate FET with no junctions nor doping concentration gradients. The doping concentration is as high as what is normally used in source and drain.
Interestingly, the use of very high doping concentrations eliminates the problem of doping fluctuations just as well as the use of undoped channels does. Having no junctions is an obvious advantage when you are considering sub-22nm nodes. It also greatly facilitates the use of semiconductor materials other than silicon.
After having worked on SOI devices for the better part of the last 30 years, I still find it is a fascinating field of research, especially if one considers the advent of quantum effects in nanoscale SOI devices.
 “Back-gate Mirror Doping for Fully Depleted Planar SOI Transistors with Thin Buried Oxide”, R. Yan et al., 2010 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), April 2010
 “Nanowire transistors without junctions”, J-P Colinge, et al., Nature Nanotechnology, Vol. 5, No. 3, pp. 225-229, 2010
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