A key enabler for the Ready for SOI Technology program is the new SOI Portal hosted on the popular ChipEstimate.com site at www.chipestimate.com/soi. The SOI Portal provides chip designers access to available design building blocks and to the companies supporting chip development on SOI processes.
“ChipEstimate.com has become a critical resource to over 26,000 registered SoC designers by providing central access to over 200 of the world’s largest IP suppliers and foundries,” said Adam TRAIDMAN, General Manager at Cadence. “Our new SOI micro-site will serve as an invaluable resource to designers wishing to explore the benefits of SOI technology for their chip design projects.”
“We are removing a barrier to industry adoption by giving all chip designers access to the benefits of SOI, not just those working for integrated device manufacturers and high-end ASIC developers,” said Horacio MENDEZ, executive director of the SOI Industry Consortium.
“Through the enablement provided by ARM’s SOI libraries and EDA tool suppliers, a vast range of synthesizable IP is now easily portable to SOI technology and physical IP can be readily ported or designed using industry standard tools.”
The SOI Industry Consortium invites all chip designers to evaluate the advantages of SOI for their next design by visiting the SOI Portal at www.chipestimate.com/soi. Digital, analog and mixed-signal IP suppliers are invited to participate in listing their offerings.
See the video “SOI Consortium at DAC: Jeff WOLF and Dave DESHARNAIS” for additional insights into the portal.
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