FD-SOI solves challenges without complicating design and manufacturing.
Designing a successful consumer-type IC requires a balanced combination of:
Figure 1 illustrates how just a few key features intrinsic to FD-SOI translate into advantages that serve those needs.
With respect to time-to-market and risk, there are essentially no specificities to designing on FD-SOI. It relies on the same flows as traditional bulk CMOS, updated to integrate FD-SOI SPICE compact models.
In addition, FD-SOI does not exhibit floating body effects — no history effect, no kink effect.
Regarding SPICE models, two approaches are proposed today: using the industry standard BSIMSOI4.x from UC Berkeley, or using models specifically optimized for ultra-thin body devices. The latter have been developed by different research centers; the next step will be integration into commercial simulators.
Most low-power design techniques can be directly ported to FD-SOI, and even enjoy improved effectiveness. For example, there is the promise of remarkable performance at lower VDD (voltage scaling), or very low leakage in retention modes.
One special case is body biasing, which, if required, can be very efficiently adapted in the form of ‘back-plane biasing’, with an ultra-thin BOx acting as a back-gate.
While multi-VT libraries can still be provided, one key benefit of FD-SOI is the undoped channel: therefore, VT adjustments are just handled differently.
Furthermore, with little intra- and inter-die dispersion of maximum frequency and leakage characteristics, FD-SOI designs do not need to be overly hardened to sustain worst cases.
If needed, the thin layer of top silicon and the BOx can be locally etched off to uncover the base silicon. With ultra-thin BOx wafers, the resulting step height between an SOI zone and a bulk zone is small enough to enable simple co-integration.