The FD SOI workshop series: A Big Success
Posted date : Dec 8, 2010

Now in their second year, these information-packed workshops are bringing in the key decision makers, and gathering ecosystem support.

In partnership with our members and complementary organizations in research, academia and industry, the SOI Industry Consortium has been organizing a series of workshops on FD SOI. The goal is to provide the highest levels of visibility throughout the industry regarding FD SOI ecosystem readiness, and to offer a forum to the fabless community and IDMs to discuss their needs for mobile and consumer applications.

Planar FD SOI offers today an evolutionary CMOS solution for 20nm for low power and high performance. Published data show VT variability reduction by 60%, and best Ion/Ioff ratios from VDD 1V down to 0.5V compared to bulk based processes. FD SOI technology enables low Vdd operation for logic and high density SRAM cells at sub-0.6V Vdd regime with excellent SNM and minimum cell size.

The Consortium’s workshops create an expert and business environment for fruitful discussions on the potential of the fully depleted IC architecture for SOC targeting 20nm and beyond. The formula is simple but extremely effective: the workshops are held at the end of major industry conferences attended by top decision makers. In addition to the conference attendees, invitations are extended to key industry representatives, opinion leaders and decision makers. Registration is free.

The response has been tremendous, with key companies making sure they send top executives and managers. In order to provide time for networking and discussions with the speakers, there is also a reception at the end, which attendees have indicated is very useful.

All FD SOI Workshop presentations are available for downloading from the SOI Industry Consortium website.

Interest worldwide

To date, workshops have been given in the US, Europe and Japan.

The first was hosted by IMEC (Leuven, Belgium) in the spring of 2009, focusing on the requirements for low power applications on FD SOI at 22nm and beyond. The second, which followed the IEDM 2009 conference (Baltimore, USA), focused on FD SOI technology readiness. The third, hosted by the University of Tokyo in September 2010, focused on the supporting ecosystem.

The fourth workshop (December 2010 in San Francisco) covered:

  • the low power and high speed technology requirements for SOC applications,
  • design infrastructure
  • and on the advantages for scaling: improved VT roll off, lowest VT variability, better subthreshold slope, better DIBL for the coming nodes, starting with 20nm.

The presentations given at the San Francisco event included:

  • Opening remarks, by Dr. Carlos Mazure – Soitec
  • Low Power and High Speed at Low Voltage for mobile applications, by Dr. Thomas Skotnicki – STMicroelectronics
  • Design flow in FD SOI, by Dr. Jean-Luc Pelloie – ARM
  • High Current drive FD SOI, by Bruce Doris – IBM
  • Ultra low power 0.3V design, by Dr. Jakub Kedzierski – MIT
  • Random device variability benchmark for bulk and FDSOI with 5 sigma data resolution, by Prof. Toshiro Hiramoto – University of Tokyo, MIRAI, Selete
  • Device Technology Requirement for wireless products, by Dr. Geoffrey Yeap and Dr. Aaron Thean – Qualcomm
  • Device Technology Requirement for GPU, by Dr. Boon-khim Liew – nVidia
  • FD SOI supply chain, by Dr. Christophe Maleville – Soitec
  • Final remarks, by Dr. Horacio Mendez – SOI Industry Consortium

About the author

Administrator administrator

You must be logged in to post a comment.