A technological tour-de-force, Soitec’s wafers for FD SOI meet all the requirements
At the 20 nm node, short channel effects and random dopant fluctuations (RDF) are the major hurdles facing the CMOS industry.
An extremely attractive solution is the planar, ultra-thin body Fully-Depleted (FD) SOI transistor. These devices are built on an ultra-thin SOI substrate, enabling an undoped channel, drastically cutting short channel effects, eliminating RDF issues and exhibiting excellent threshold voltage (Vt) control.
However, FD SOI architectures require wafers with an extremely thin and uniform top silicon layer. For delivered substrates, the top silicon layer is 10-20 nm thick, compared to wafers for today’s high-volume Partially Depleted (PD) SOI applications, which require top silicon that is 70-90 nm thick. The finished FD SOI transistor channel is 5-7 nm thick, as some silicon is consumed in the chip manufacturing process.
Soitec’s Smart Cut technology is used to make mainstream thin SOI wafers for high-volume applications. We apply that same technology to manufacture wafers for FD SOI.
As such, we use the mature Smart Cut process flow, the same toolset, and leverage over 10 years of continual research, learning and high-volume manufacturing expertise. There is no process disruption. There are no technical nor industrial showstoppers. Soitec’s Smart Cut technology’s unique capabilities are fully leveraged here to generate ultra-thin layers with high quality and uniformity.
Thickness uniformity is a key parameter in controlling Vt variation in planar FD SOI devices. Typical uniformity requirements include on-wafer uniformity and wafer-to-wafer uniformity. Together, they are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the sub-nanometer (<1 nm) range for the UT SOI layer for all wafers and all sites in order to meet the FD specifications.
Leveraging hydrogen implantation, Smart Cut technology delivers on-wafer uniformity below the 1 nm range. Current wafers for FD SOI are being produced with 12 nm top silicon and uniformity control at +/- 5 Å (0.5 nm) for wafer-to-wafer distribution. Under the Soitec program for continuous improvement of our APC (advanced process control) strategy, we fully expect to reach wafer-to-wafer uniformity of +/- 2 Å (0.2 nm). The roadmap is now in place for high-volume manufacturing, producing wafers for FD SOI with top silicon uniformity control LTTV (all wafers, all sites) at +/- 5 Å (0.5 nm).
A promising usage of FD SOI involves the option of a very thin insulating BOX layer: just 25 nm thick (compared to 145 nm for today’s high-volume SOI). The “thin” BOX option suppresses lateral electrostatic coupling and enables increased performance through bias management of the channel. It is currently available as a pre-production product.
Soitec’s thin-BOX products are manufactured using the same platform as today’s standard BOX SOI wafers. There is no impact on thickness uniformity or defectivity. From a wafer manufacturing standpoint, the BOX thickness and top silicon thickness are independent parameters: one can be adjusted without degrading the quality of the other.
With the merits firmly established, FD SOI devices offer the advantage of merging general purpose (G) and low power (LP) technology in a cost-effective platform for a wide range of applications.
There were once some in the industry who questioned whether SOI wafers could ever be made to the exacting parameters of FD SOI. Any doubts can now be completely laid to rest: the ramp to production volumes of wafers for FD SOI has begun. The standard in SOI manufacturing, Smart Cut technology is used in production by several suppliers. Therefore, the supply of substrates for FD SOI will be ready to serve all potential applications at the appropriate substrate cost.
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