Thinking Thin: NXP’s EZ-HV-SOI
Posted date : Dec 13, 2010

First announced a decade ago, NXP’s EZ-HV™ is process technology for the production of commercial high-voltage (HV) SOI-enabled ICs.  It is at the heart of NXP’s GreenChip technology, and is ideal for implementing optimal solutions for a wide range of lighting applications. In high-power systems, it allows sophisticated control logic and high voltage drive circuits to be integrated into a single IC (replacing the separate high and low voltage chips), halving the cost of the overall unit.

It represents a radical departure from “thick SOI” solutions, in which a 10 to 20 micron layer of silicon overlaying an insulating material limits the electric field strength to prevent a regenerative, killer effect called ‘avalanche breakdown’.

Instead, the EZ-HV process uses SOI wafers with a relatively thin layer of top silicon (only 0.5 microns thick), which is much cheaper to produce. Even with 650 volts applied across this layer there is still insufficient distance between the upper and lower layers of the silicon for charge carriers to be accelerated to avalanche breakdown energy levels.

Other advantages include:

  • lower cost
  • higher integration density
  • latch-up immunity, even with multiple power components on a single chip
  • significantly reduced parasitic capacitance for far faster switching
  • RDS(on) values halved enables handling of higher currents
  • drift region fully depleted doubles effectiveness of RESURF, simplifying high-voltage design trade-offs

Cross Section of EZ-HV LDMOS Structure: Producing this critical high-voltage component requires the use of only 13 mask steps, making the production of basic EZ-HV ICs cost-effective even for price sensitive applications.

About the author

Administrator administrator

You must be logged in to post a comment.